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Message-ID: <23821511.2233195.1461705654070.JavaMail.yahoo@mail.yahoo.com>
Date: Tue, 26 Apr 2016 21:20:54 +0000 (UTC)
From: <apingis@...nwall.net>
To: "john-dev@...ts.openwall.com" <john-dev@...ts.openwall.com>
Subject: Re: USB-FPGA development
Hi Lukas,
On Tuesday, April 26, 2016 10:32 PM, Lukas Odzioba <lukas.odzioba@...il.com> wrote:
> Hi Denis,
> could you please mention specific benchmark IO numbers?
> For very slow hashes we would be ok with 10 000 c/s times password length - let's say 10 it is 800kB per board.
> For fast hashes we have a bottleneck even on GPUs with GB/s transfers,
> so it is not a big deal I guess, it just narrows number of potential hashes which we do have plenty.
At test site, it displays 20 MB/s. There's small increase if FPGA's buffers doubled, quadrupled etc. and absolute maximum (achieved if host sends/receives in 512K pieces) is about 30 MB/s.
> Is your code (and underlying libraries) thread safe?
So far I didn't implement parallel processing of several boards. I'm considering usage of asynchronous USB transfer functions, or usage of OpenMP, or several threads or processes. So far it's a standalone test application and I'm yet unsure how exactly it would integrate into JtR code. Any suggestions are welcome.
> Does increasing alignment over 8 bytes makes any difference?
There's no difference in I/O performance. 8-byte alignment comes from FIFO width on FPGA side (the end of FIFO that is opposite to I/O pins), you can change it so input data better fits application logic.
> Will you be able to do computations and fetch data simoultaneously on fpga side with current code?
Yes, while some pieces of virtual hardware operate I/O pins and store/fetch data to internal FIFOs, at the same time other FPGA logic operate at other ends of FIFOs and do computations.
> Did you test in on more than 1 board?
Yes I tested it. Right now it's successfully doing sequential usb_bulk_transfer() blocking calls.
Denis
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