[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CABob6ioLhJYp9G30Z3SNLv4Vtc_7wee7kbztBRoucdAJ6g5ccA@mail.gmail.com>
Date: Tue, 26 Apr 2016 21:31:34 +0200
From: Lukas Odzioba <lukas.odzioba@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: USB-FPGA development
2016-04-26 15:16 GMT+02:00 <apingis@...nwall.net>:
> There are issues on integration of ZTEX USB-FPGA applications and JtR. The features of the device are:
> - low I/O speed (if compared to e.g. GPU). That's a problem if there are fast to compute hashes.
> - the device doesn't have much memory. Actually each chip has 0.5MB of internal memory and there's no other memory on the device. That seems to be enough for many hash types. However when it comes to an idea to implement on-chip candidate password generator, there's no enough memory to store wordlist or charset data.
Hi Denis,
could you please mention specific benchmark IO numbers?
For very slow hashes we would be ok with 10 000 c/s times password
length - let's say 10 it is 800kB per board.
For fast hashes we have a bottleneck even on GPUs with GB/s transfers,
so it is not a big deal I guess, it just narrows number of potential
hashes which we do have plenty.
Is your code (and underlying libraries) thread safe?
Does increasing alignment over 8 bytes makes any difference?
Will you be able to do computations and fetch data simoultaneously on
fpga side with current code?
Did you test in on more than 1 board?
Thanks,
Lukas
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
