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Message-ID: <942773907.1964752.1461676564275.JavaMail.yahoo@mail.yahoo.com>
Date: Tue, 26 Apr 2016 13:16:04 +0000 (UTC)
From: <apingis@...nwall.net>
To: "john-dev@...ts.openwall.com" <john-dev@...ts.openwall.com>
Subject: USB-FPGA development
Hi,
I'm doing an application development for FPGA, looking forward to integrate it into JtR.
The hardware is ZTEX USB-FPGA module 1.15y.
The task to implement a communication between host software and USB-FPGA module appeared to be time consuming because of following reasons:
- Ztex SDK doesn't include C host software library. There's Java library only;
- There's no examples or applications that communicate to Ztex board at high speed. E.g. various applications for Bitcoin Mining operate at speed no more than 0.5 MB/s;
- The hardware is a Multi-FPGA board with 4 FPGA chips and 1 USB device controller. FPGA chips don't have independent communication interfaces and at the first glance they don't look like independent devices. So it's an application developer's task to design a system of properly arranged I/O so host and FPGAs communicate in some ordered manner.
I've extracted a sub-project, ztex/examples/inouttraffic. That can be used as a starting point for creation of Ztex USB-FPGA applications.
The project is available at
https://github.com/Apingis/ztex_inouttraffic
The project includes HDL(Verilog) part, USB device controller's firmware and C host software.
There are issues on integration of ZTEX USB-FPGA applications and JtR. The features of the device are:
- low I/O speed (if compared to e.g. GPU). That's a problem if there are fast to compute hashes.
- the device doesn't have much memory. Actually each chip has 0.5MB of internal memory and there's no other memory on the device. That seems to be enough for many hash types. However when it comes to an idea to implement on-chip candidate password generator, there's no enough memory to store wordlist or charset data.
Denis
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