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Message-ID: <1340791807.24392.YahooMailNeo@web161301.mail.bf1.yahoo.com>
Date: Wed, 27 Jun 2012 03:10:07 -0700 (PDT)
From: deepika dutta <deepikadutta_19@...oo.com>
To: "john-dev@...ts.openwall.com" <john-dev@...ts.openwall.com>
Subject: Re: mschap-v2 conversion
yaa i know that gate count numbers have been provided by few researchers and JTR has i believe the lowest gate count presently (or is there some other also?) But there is no mention of maximum speedup one can achieve with bitslicing for say a 64 bit processor with current lowest gate count implementation? Are any figures possible for the maxima? or will depend on how much further one can optimize.
Cheers,
Deepika
________________________________
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Sent: Wednesday, June 27, 2012 3:14 PM
Subject: Re: [john-dev] mschap-v2 conversion
On Wed, Jun 27, 2012 at 01:35:06AM -0700, deepika dutta wrote:
> I don't find even in literature somebody giving any figure on how much speedup bitslicing can achieve,
Eli Biham's paper had some specific numbers. The gate count per S-box
has been more than halved since then and modern CPUs have wider than
64-bit vectors, though - so greater speedups are being achieved now.
Alexander
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