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Message-ID: <20120627111615.GB17288@openwall.com>
Date: Wed, 27 Jun 2012 15:16:15 +0400
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: mschap-v2 conversion
On Wed, Jun 27, 2012 at 03:10:07AM -0700, deepika dutta wrote:
> yaa i know that gate count numbers have been provided by few researchers and JTR has i believe the lowest gate count presently (or is there some other also?) But there is no mention of maximum speedup one can achieve with bitslicing for say a 64 bit processor with current lowest gate count implementation? Are any figures possible for the maxima? or will depend on how much further one can optimize.
You can calculate theoretical speedup by carefully counting clock cycles
for a particular CPU for two implementations (per DES encryption
performed), but then, if done right, it's the same as actually running
the two implementations and comparing actual speeds. In fact, the
speedup numbers in Eli Biham's paper were from actually running the code
on a particular Alpha CPU.
Alexander
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