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Message-ID: <BANLkTin7A=Y8=V5W1MMvy7z+ORYjz9Va3Q@mail.gmail.com> Date: Thu, 19 May 2011 18:32:33 -0300 From: Yuri Gonzaga <yuriggc@...il.com> To: crypt-dev@...ts.openwall.com Subject: Re: alternative approach Hi! I did the first attempt. I think I spent more time than I expected mainly because the adaptation to Xilinx dev environment. It is composed of a state machine to read the "n" input, calculate the rounds and then output "l", "r" and "s" (byte-by-byte). I put a directive `define to parameterize how much rounds are done per single clock cycle. The state machine has 8 states, but only 2 are related to rounds calculation. For NROUNDS = 2, synthesis results (Target Device: Virtex6 xc6vlx75t-3ff484): Device Utilization Summary (estimated values) [-] <?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)> Logic Utilization Used Available Utilization Number of Slice Registers 35 93120 0% Number of Slice LUTs 131 46560 0% Number of fully used LUT-FF pairs 35 131 26% Number of bonded IOBs 14 240 5% Number of BUFG/BUFGCTRLs 2 32 6% Maximum frequency: 261.356MHz For NROUNDS = 4 (same target device): Device Utilization Summary (estimated values) [-] <?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)> Logic Utilization Used Available Utilization Number of Slice Registers 35 93120 0% Number of Slice LUTs 183 46560 0% Number of fully used LUT-FF pairs 35 183 19% Number of bonded IOBs 14 240 5% Number of BUFG/BUFGCTRLs 2 32 6% Maximum frequency: 147.432MHz About the pipelining, how can we deal with the fact that there are dependencies between r, l and s in calculations? Will each stage have to store locally r, l and s? The verilog code is attached, including simulation. Regards, Yuri Gonzaga Content of type "text/html" skipped Download attachment "slow_key_setup1.v" of type "application/octet-stream" (3311 bytes) Download attachment "testbench.v" of type "application/octet-stream" (1076 bytes)
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