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Message-ID: <87o85snrj7.fsf@oldenburg.str.redhat.com>
Date: Tue, 07 Dec 2021 20:28:28 +0100
From: Florian Weimer <fweimer@...hat.com>
To: Markus Wichmann <nullplan@....net>
Cc: musl@...ts.openwall.com
Subject: Re: [PATCH] ppc64: check for AltiVec in setjmp/longjmp
* Markus Wichmann:
> That said, architecturally it will work either way. We are only talking
> about an implementation detail, and both IBM's and Freescale's/NXP's
> documentation is very cagey about revealing any of those.
We do have source code for one implementation.
| -- bcl 20,31,$+4 is special case. not a subroutine call, used to get next instruction address, should not be placed on link stack.
| iu4_bo_d( 6 to 10) <= iu3_instr_pri( 6 to 10);
| iu4_bi_d(11 to 15) <= iu3_instr_pri(11 to 15);
|
| iu4_getNIA <= iu4_opcode_q(0 to 5) = "010000" and
| iu4_bo_q(6 to 10) = "10100" and
| iu4_bi_q(11 to 15) = "11111" and
| iu4_bd(EFF_IFAR'left to 61) = 1 and
| iu4_aa_q = '0' and
| iu4_lk_q = '1' ;
<https://github.com/openpower-cores/a2i/blob/96299300abca65a074c635204a163e10569ee9b7/rel/src/vhdl/work/iuq_bp.vhdl#L880>
I suspect “iu4_bd(EFF_IFAR'left to 61) = 1” matches 4 exactly (the
lowest four bits of the offset are not encoded in the instruction
because they are always zero). But I don't know any VHDL.
Thanks,
Florian
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