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Message-ID: <X+Sh+l+E8az2Ye1O@sx9>
Date: Thu, 24 Dec 2020 15:13:14 +0100
From: Fredrik Noring <noring@...rew.org>
To: musl@...ts.openwall.com
Subject: [PATCH] MIPS: Use ".set mips2" to emulate LL/SC for the R5900 too
Hi,
GAS treats the R5900 as MIPS III, with some modifications. The MIPS III
designation means that Musl will try to assemble the LL and SC instructions,
even though they are not implemented in the R5900. GAS will therefore
produce the following errors:
Error: opcode not supported on this processor: r5900 (mips3) `ll $3,0($5)'
Error: opcode not supported on this processor: r5900 (mips3) `sc $3,0($5)'
The MIPS II ISA override as used here enables the kernel to trap and
emulate the LL and SC instructions, as required.
This change has been tested by compiling Musl 1.2.1 with a GCC 10.2.0
cross-compiler for the mipsr5900el-unknown-linux-musl target under Gentoo.
It's equivalent to GNU C library commit 8e3c00db16fc ("MIPS: Use
`.set mips2' to emulate LL/SC for the R5900 too").
diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
index 1248d177..ef21cb23 100644
--- a/arch/mips/atomic_arch.h
+++ b/arch/mips/atomic_arch.h
@@ -8,7 +8,8 @@
static inline int a_ll(volatile int *p)
{
int v;
-#if __mips < 2
+ /* The R5900 reports itself as MIPS III but it does not have LL/SC. */
+#if __mips < 2 || defined(_MIPS_ARCH_R5900)
__asm__ __volatile__ (
".set push ; .set mips2\n\t"
"ll %0, %1"
@@ -26,7 +27,8 @@ static inline int a_ll(volatile int *p)
static inline int a_sc(volatile int *p, int v)
{
int r;
-#if __mips < 2
+ /* The R5900 reports itself as MIPS III but it does not have LL/SC. */
+#if __mips < 2 || defined(_MIPS_ARCH_R5900)
__asm__ __volatile__ (
".set push ; .set mips2\n\t"
"sc %0, %1"
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