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Message-ID: <1439743112.9803.40.camel@inria.fr>
Date: Sun, 16 Aug 2015 18:38:32 +0200
From: Jens Gustedt <jens.gustedt@...ia.fr>
To: musl@...ts.openwall.com
Subject: Re: [PATCH] replace a mfence instruction by an xchg
instruction
Am Sonntag, den 16.08.2015, 12:28 -0400 schrieb Rich Felker:
> On Sat, Aug 15, 2015 at 08:51:41AM +0200, Jens Gustedt wrote:
> > according to the wisdom of the Internet, e.g
> >
> > https://peeterjoot.wordpress.com/2009/12/04/intel-memory-ordering-fence-instructions-and-atomic-operations/
> >
> > a mfence instruction is about 3 times slower than an xchg instruction.
>
> I can't find where the article makes this claim. Could you point out
> what part you're referring to?
I read this in the section that says "Performance comparsion".
There it says something like "lock xchg" 16x baseline and "smfence"
47-67 x baseline. But perhaps I am misinterpreting things.
Jens
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