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Message-ID: <20120210191209.GA17416@openwall.com>
Date: Fri, 10 Feb 2012 23:12:09 +0400
From: Solar Designer <solar@...nwall.com>
To: musl@...ts.openwall.com
Subject: Re: tough choice on thread pointer initialization issue
On Fri, Feb 10, 2012 at 12:00:15PM -0500, Rich Felker wrote:
> On Fri, Feb 10, 2012 at 02:42:52PM +0400, Solar Designer wrote:
> > All of these execute in 1000 cycles total as well. With "w" forms of
> > the instructions there are extra prefixes, so I think these should
> > better be avoided, even though there's no slowdown from them on this CPU.
>
> I had no idea it was even valid to use the non-w-prefix forms with
> segment registers. Learned something new. Are the high bits just
> discarded (when writing) and zeroed (when reading)?
Yes.
Frankly, I am not sure how portable this is exactly. The Linux kernel
uses these short forms unconditionally (although there are also a few
instances of "movw"), whereas glibc somehow uses them on 686+ only - see
nptl/sysdeps/i386/tls.h vs. nptl/sysdeps/i386/i686/tls.h. The latter
has this comment:
/* Macros to load from and store into segment registers. We can use
the 32-bit instructions. */
My guess is that this is one of those things that was always this way,
but was only documented much later - starting with Pentium Pro maybe?
We can download some PDFs from Intel to confirm when this appeared
officially. I'd start with those for PPro.
There were several things documented at about this time - e.g., the SALC
instruction that was available since 8086 (including clones), but was
only documented by Intel starting with Pentium Pro.
glibc is probably too careful in limiting this to 686+.
Well, I wouldn't be too surprised if some pre-686 CPU did not zero out
the high bits on read from segment registers into 32-bit registers.
If we're merely copying the value into another segment register, this
does not matter, but for the non-zero test it does...
Alexander
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