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Message-ID: <99FC4B6EFCEFD44486C35F4C281DC6732143F769@ORSMSX107.amr.corp.intel.com>
Date: Mon, 20 Aug 2018 14:45:10 +0000
From: "Schaufler, Casey" <casey.schaufler@...el.com>
To: Jann Horn <jannh@...gle.com>
CC: Kernel Hardening <kernel-hardening@...ts.openwall.com>, kernel list
<linux-kernel@...r.kernel.org>, linux-security-module
<linux-security-module@...r.kernel.org>, "selinux@...ho.nsa.gov"
<selinux@...ho.nsa.gov>, "Hansen, Dave" <dave.hansen@...el.com>, "Dock,
Deneen T" <deneen.t.dock@...el.com>, "kristen@...ux.intel.com"
<kristen@...ux.intel.com>, Arjan van de Ven <arjan@...ux.intel.com>
Subject: RE: [PATCH RFC v2 2/5] X86: Support LSM determination of
side-channel vulnerability
> -----Original Message-----
> From: Jann Horn [mailto:jannh@...gle.com]
> Sent: Friday, August 17, 2018 4:55 PM
> To: Schaufler, Casey <casey.schaufler@...el.com>
> Cc: Kernel Hardening <kernel-hardening@...ts.openwall.com>; kernel list
> <linux-kernel@...r.kernel.org>; linux-security-module <linux-security-
> module@...r.kernel.org>; selinux@...ho.nsa.gov; Hansen, Dave
> <dave.hansen@...el.com>; Dock, Deneen T <deneen.t.dock@...el.com>;
> kristen@...ux.intel.com; Arjan van de Ven <arjan@...ux.intel.com>
> Subject: Re: [PATCH RFC v2 2/5] X86: Support LSM determination of side-
> channel vulnerability
>
> On Sat, Aug 18, 2018 at 12:17 AM Casey Schaufler
> <casey.schaufler@...el.com> wrote:
> >
> > From: Casey Schaufler <cschaufler@...alhost.localdomain>
> >
> > When switching between tasks it may be necessary
> > to set an indirect branch prediction barrier if the
> > tasks are potentially vulnerable to side-channel
> > attacks. This adds a call to security_task_safe_sidechannel
> > so that security modules can weigh in on the decision.
> >
> > Signed-off-by: Casey Schaufler <casey.schaufler@...el.com>
> > ---
> > arch/x86/mm/tlb.c | 12 ++++++++----
> > 1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> > index 6eb1f34c3c85..8714d4af06aa 100644
> > --- a/arch/x86/mm/tlb.c
> > +++ b/arch/x86/mm/tlb.c
> > @@ -7,6 +7,7 @@
> > #include <linux/export.h>
> > #include <linux/cpu.h>
> > #include <linux/debugfs.h>
> > +#include <linux/security.h>
> >
> > #include <asm/tlbflush.h>
> > #include <asm/mmu_context.h>
> > @@ -270,11 +271,14 @@ void switch_mm_irqs_off(struct mm_struct *prev,
> struct mm_struct *next,
> > * threads. It will also not flush if we switch to idle
> > * thread and back to the same process. It will flush if we
> > * switch to a different non-dumpable process.
> > + * If a security module thinks that the transition
> > + * is unsafe do the flush.
> > */
> > - if (tsk && tsk->mm &&
> > - tsk->mm->context.ctx_id != last_ctx_id &&
> > - get_dumpable(tsk->mm) != SUID_DUMP_USER)
> > - indirect_branch_prediction_barrier();
> > + if (tsk && tsk->mm && tsk->mm->context.ctx_id != last_ctx_id) {
> > + if (get_dumpable(tsk->mm) != SUID_DUMP_USER ||
> > + security_task_safe_sidechannel(tsk) != 0)
> > + indirect_branch_prediction_barrier();
> > + }
>
> When you posted v1 of this series, I asked:
>
> | Does this enforce transitivity? What happens if we first switch from
> | an attacker task to a task without ->mm, and immediately afterwards
> | from the task without ->mm to a victim task? In that case, whether a
> | flush happens between the attacker task and the victim task depends on
> | whether the LSM thinks that the mm-less task should have access to the
> | victim task, right?
>
> Have you addressed that? I don't see it...
Nope. That's going to require maintaining state about all the
tasks in the chain that might still have cache involvement.
A -> B -> C -> D
If B and C don't do anything cacheworthy D could conceivably attack A.
The amount of state required to detect this case would be prohibitive.
I think that if you're sufficiently concerned about this case you should just
go ahead and set the barrier. I'm willing to learn something that says I'm
wrong.
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