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Message-ID: <alpine.DEB.2.20.1803141051210.14471@nuc-kabylake> Date: Wed, 14 Mar 2018 10:54:58 -0500 (CDT) From: Christopher Lameter <cl@...ux.com> To: Peter Zijlstra <peterz@...radead.org> cc: Thomas Garnier <thgarnie@...gle.com>, Herbert Xu <herbert@...dor.apana.org.au>, "David S . Miller" <davem@...emloft.net>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, "H . Peter Anvin" <hpa@...or.com>, Josh Poimboeuf <jpoimboe@...hat.com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Kate Stewart <kstewart@...uxfoundation.org>, Arnd Bergmann <arnd@...db.de>, Philippe Ombredanne <pombredanne@...b.com>, Arnaldo Carvalho de Melo <acme@...hat.com>, Andrey Ryabinin <aryabinin@...tuozzo.com>, Matthias Kaehlcke <mka@...omium.org>, Kees Cook <keescook@...omium.org>, Tom Lendacky <thomas.lendacky@....com>, "Kirill A . Shutemov" <kirill.shutemov@...ux.intel.com>, Andy Lutomirski <luto@...nel.org>, Dominik Brodowski <linux@...inikbrodowski.net>, Borislav Petkov <bp@...en8.de>, Borislav Petkov <bp@...e.de>, "Rafael J . Wysocki" <rjw@...ysocki.net>, Len Brown <len.brown@...el.com>, Pavel Machek <pavel@....cz>, Juergen Gross <jgross@...e.com>, Alok Kataria <akataria@...are.com>, Steven Rostedt <rostedt@...dmis.org>, Tejun Heo <tj@...nel.org>, Dennis Zhou <dennisszhou@...il.com>, Boris Ostrovsky <boris.ostrovsky@...cle.com>, David Woodhouse <dwmw@...zon.co.uk>, Alexey Dobriyan <adobriyan@...il.com>, "Paul E . McKenney" <paulmck@...ux.vnet.ibm.com>, Andrew Morton <akpm@...ux-foundation.org>, Nicolas Pitre <nicolas.pitre@...aro.org>, Randy Dunlap <rdunlap@...radead.org>, "Luis R . Rodriguez" <mcgrof@...nel.org>, Christopher Li <sparse@...isli.org>, Jason Baron <jbaron@...mai.com>, Ashish Kalra <ashish@...estacks.com>, Kyle McMartin <kyle@...hat.com>, Dou Liyang <douly.fnst@...fujitsu.com>, Lukas Wunner <lukas@...ner.de>, Petr Mladek <pmladek@...e.com>, Sergey Senozhatsky <sergey.senozhatsky.work@...il.com>, Masahiro Yamada <yamada.masahiro@...ionext.com>, Ingo Molnar <mingo@...nel.org>, Nicholas Piggin <npiggin@...il.com>, Cao jin <caoj.fnst@...fujitsu.com>, "H . J . Lu" <hjl.tools@...il.com>, Paolo Bonzini <pbonzini@...hat.com>, Radim Krčmář <rkrcmar@...hat.com>, Joerg Roedel <joro@...tes.org>, Dave Hansen <dave.hansen@...ux.intel.com>, Rik van Riel <riel@...hat.com>, Jia Zhang <qianyue.zj@...baba-inc.com>, Jiri Slaby <jslaby@...e.cz>, Kyle Huey <me@...ehuey.com>, Jonathan Corbet <corbet@....net>, Matthew Wilcox <mawilcox@...rosoft.com>, Michal Hocko <mhocko@...e.com>, Rob Landley <rob@...dley.net>, Baoquan He <bhe@...hat.com>, Daniel Micay <danielmicay@...il.com>, Jan H . Schönherr <jschoenh@...zon.de>, x86@...nel.org, linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org, virtualization@...ts.linux-foundation.org, xen-devel@...ts.xenproject.org, linux-arch@...r.kernel.org, linux-sparse@...r.kernel.org, kvm@...r.kernel.org, linux-doc@...r.kernel.org, kernel-hardening@...ts.openwall.com Subject: Re: [PATCH v2 06/27] x86/entry/64: Adapt assembly for PIE support On Wed, 14 Mar 2018, Peter Zijlstra wrote: > On Tue, Mar 13, 2018 at 01:59:24PM -0700, Thomas Garnier wrote: > > @@ -1576,7 +1578,9 @@ first_nmi: > > addq $8, (%rsp) /* Fix up RSP */ > > pushfq /* RFLAGS */ > > pushq $__KERNEL_CS /* CS */ > > - pushq $1f /* RIP */ > > + pushq %rax /* Support Position Independent Code */ > > + leaq 1f(%rip), %rax /* RIP */ > > + xchgq %rax, (%rsp) /* Restore RAX, put 1f */ > > iretq /* continues at repeat_nmi below */ > > UNWIND_HINT_IRET_REGS > > 1: > > Urgh, xchg with a memop has an implicit LOCK prefix. this_cpu_xchg uses no lock cmpxchg as a replacement to reduce latency. >From linux/arch/x86/include/asm/percpu.h /* * xchg is implemented using cmpxchg without a lock prefix. xchg is * expensive due to the implied lock prefix. The processor cannot prefetch * cachelines if xchg is used. */ #define percpu_xchg_op(var, nval) \ ({ \ typeof(var) pxo_ret__; \ typeof(var) pxo_new__ = (nval); \ switch (sizeof(var)) { \ case 1: \ asm("\n\tmov "__percpu_arg(1)",%%al" \ "\n1:\tcmpxchgb %2, "__percpu_arg(1) \ "\n\tjnz 1b" \ : "=&a" (pxo_ret__), "+m" (var) \ : "q" (pxo_new__) \ : "memory"); \ break; \ case 2: \ asm("\n\tmov "__percpu_arg(1)",%%ax" \ "\n1:\tcmpxchgw %2, "__percpu_arg(1) \ "\n\tjnz 1b" \ : "=&a" (pxo_ret__), "+m" (var) \ : "r" (pxo_new__) \ : "memory"); \ break; \ case 4: \ asm("\n\tmov "__percpu_arg(1)",%%eax" \ "\n1:\tcmpxchgl %2, "__percpu_arg(1) \ "\n\tjnz 1b" \ : "=&a" (pxo_ret__), "+m" (var) \ : "r" (pxo_new__) \ : "memory"); \ break; \ case 8: \ asm("\n\tmov "__percpu_arg(1)",%%rax" \ "\n1:\tcmpxchgq %2, "__percpu_arg(1) \ "\n\tjnz 1b" \ : "=&a" (pxo_ret__), "+m" (var) \ : "r" (pxo_new__) \ : "memory"); \ break; \ default: __bad_percpu_size(); \ } \ pxo_ret__; \
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