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Message-ID: <20160815163929.GI22320@e104818-lin.cambridge.arm.com>
Date: Mon, 15 Aug 2016 17:39:29 +0100
From: Catalin Marinas <catalin.marinas@....com>
To: Mark Rutland <mark.rutland@....com>
Cc: Will Deacon <will.deacon@....com>, James Morse <james.morse@....com>,
Kees Cook <keescook@...omium.org>,
linux-arm-kernel@...ts.infradead.org,
kernel-hardening@...ts.openwall.com
Subject: Re: [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel
execution
On Mon, Aug 15, 2016 at 12:18:58PM +0100, Mark Rutland wrote:
> On Fri, Aug 12, 2016 at 04:27:43PM +0100, Catalin Marinas wrote:
> > diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
> > index b5c3933ed441..9283e6b247f9 100644
> > --- a/arch/arm64/include/uapi/asm/ptrace.h
> > +++ b/arch/arm64/include/uapi/asm/ptrace.h
> > @@ -52,6 +52,8 @@
> > #define PSR_Z_BIT 0x40000000
> > #define PSR_N_BIT 0x80000000
> >
> > +#define _PSR_PAN_BIT 22
>
> Given this is under uapi/, shouldn't we lose the leading underscore to align
> with other PSR_* definitions?
>
> Or should we not have this under uapi/?
I moved it to the non-uapi ptrace.h.
> [...]
>
> > + mrs lr, ttbr0_el1
> > + tst lr, #0xffff << 48 // Check for the reserved ASID
>
> Did we not have a regular register spare here? Not a problem, but using the lr
> here stands out as unusual.
LR is a general purpose register, we just have an alias for it. I've
replaced it with x21 so that it doesn't stand out.
--
Catalin
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