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Message-ID: <CA+EaD-bnEGXXyGc0fXYV_QNqQrQYt4gGHv55Z31OFnNmw-r68A@mail.gmail.com>
Date: Sun, 26 Jul 2015 20:51:42 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: Re: ztex 1.15y boards, pre-development
On 26 July 2015 at 20:12, Aleksey Cherepanov <lyosha@...nwall.com> wrote:
>
> But for me, it segfaulted first several runs and then it fails on every
> run:
>
> S[0][0] = 0xd1310ba6 0xd131f12c <<< failure
> S[0][1] = 0x98dfb5ac 0x98dfb5ac ok
> S[0][2] = 0x2ffd72db 0x2ffd72db ok
> S[0][3] = 0xd01adfb7 0xd01adfb7 ok
> S[0][4] = 0xb8e1afed 0xb8e1afed ok
> S[0][5] = 0x6a267e96 0x6a267e96 ok
> S[0][6] = 0xba7c9045 0xba7c9045 ok
> S[0][7] = 0xf12c7f99 0xf12c7f99 ok
>
Hm... this looks like first word written by FPGA is the last one from the
previous read/write cycle (0xf12c). And it's not the same problem as I get
on my board :(
I was trying to implement data transfers using BRAMs but I encountered more
problems: one being that TRM claims writing to FIFO is possible on every
rising clock edge as long as SLWR is asserted (active when 0). That is used
in intraffic example. However, it doesn't work for me. I have to do it in
two cycles so data gets written to FIFO on rising edge of SLRW. That is how
asynchronous writes work but I configure IFCONFIG register in synchronous
mode. Similar is claimed for reads, you can read one word from FIFO on each
clock cycle while SLRD is asserted (commented code in the repo, and that
does work). I also tried various FPGA designs, some of them deliberately
producing wrong output (writing FIFO only lower word of each dword from
BRAM) and I just get more inconsistent results.
I don't think I can figure out this before CMIYC given that I don't have
access to JTAG nor to oscilloscope and time I can allocate is limited to 5
- 10 hours per week. But I'll try nevertheless, maybe I'm not seeing
something obvious.
> Also I noticed that only 1 led on board became black, so I think only
> 1 fpga chip got bitstream
>
Yes, that's correct. I didn't bother with figuring out how to use all FPGAs
until I don't have working design on just one (SDK comes with support for
java, cgminer has driver for C, I just briefly looked at it).
Katja
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