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Message-ID: <CA+EaD-afOEC28VEGO8ws6MfjcqB1UxrK0kOcQwWwSD+gHz14=g@mail.gmail.com>
Date: Mon, 14 Oct 2013 19:09:58 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard: bcrypt
Hello,
So far all clocks I tried that are higher than 100 MHz fail timing analysis
(200 MHz, 125 MHz, 112 MHz). Synthesis reports maximum frequency of
164.690MHz but it seems it's not possible to implement it.
If I try to generate bitstream in Xilinx Platform Studio, bitstream is not
created if timing analysis fails. However, if I create it in PlanAhead than
it is created even though timing analysis isn't met. And on Parallella
board it worked for 150 MHz which I found very weird.
I will continue working on implementing multiple bcrypt cores using 100 MHz
clock and I'll return to clock problems after that is done.
Katja
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