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Message-ID: <CA+EaD-ZhOvQjCz7TaCTWVovM6KSGr=hFXXr1M-6apV8vso-eTg@mail.gmail.com>
Date: Wed, 11 Sep 2013 14:00:45 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard / Parallella: bcrypt
On Tue, Sep 10, 2013 at 12:14 PM, Katja Malvoni <kmalvoni@...il.com> wrote:
> I'm travelling at the moment and my laptop battery doesn't work so I don't
> have exact numbers, I'll have them in the evening.
>
I'm sorry about delay, but when I finally arrived home I was too tired to
do anything.
What I remember is that synthesis report says maximum frequency is around
> 77 MHz when I create parallella bitstream.
Correct number is 80 MHz
> when I generate bitstream for zedboard without parallella, synthesis
> reports around 245 MHz.
This one is 272 MHz.
> When I added bcrypt IP in parallella system I connected bus to FCLK0 which
> operates on 200 MHz and I use that clock in always @ (posedge clk) so I
> think I can't go beyond that. There are 3 other clock pins but all of them
> are less than 200 MHz. I think that one of them might be changed without
> consequences for Epiphany.
>
FCLK0 frequency is 100 MHz and that corresponds with observed speed. I
tried connecting it to the 200 MHz clock pin but it doesn't produce correct
result.
If HDMI support is added than 2 clock pins are different when compared to
headless system. Parallella platform reference design states that the
system should be functional even with different set of clock frequencies as
long as FCLK0 is unchanged.
On Mon, Sep 9, 2013 at 11:12 PM, Solar Designer <solar@...nwall.com> wrote:
> Given the current FPGA
> utilization with and without this one bcrypt core added, roughly how
> many such bcrypt cores would fit?
>
I forgot to answer this question earlier. I'm not completely sure. The
problem is that I connect IP core to general purpose master bus and I have
only one master bus available. So this means all cores will be connected to
that same bus. But the problem is that no communication can be done in
parallel. I'm not sure how many would fit given the utilization since DMA
and 3 AXI buses are implemented in FPGA as well so part of utilization
comes from there.
Utilization when having only bcrypt without Parallella is (this is
synthesis estimation):
Register 1%
LUT 3%
IO 5%
Block Memor 2% (I'm putting initial key, expanded key and salt in
bram as well because host writes them to bram)
BUFG/BUFGCTRL 3%
With bcrypt and Parallella:
Register 10%
LUT 20%
Slice 39%
IO 39%
RAMB36E1 3%
RAMB18E1 1%
BUFR 6%
BUFG 28%
Parallella only:
Register 3%
LUT 5%
Slice 9%
IO 39%
RAMB36E1 2%
RAMB18E1 1%
BUFR 6%
BUFG 25%
Katja
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