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Message-ID: <CA+EaD-axLbtpBaSG=5Xn5o7M1zUSncoSsJUkAzyF8Tz_pL5e-A@mail.gmail.com>
Date: Tue, 10 Sep 2013 12:14:29 +0200
From: Katja Malvoni <kmalvoni@...il.com>
To: john-dev@...ts.openwall.com
Subject: Re: ZedBoard / Parallella: bcrypt
On Sep 9, 2013 11:13 PM, "Solar Designer" <solar@...nwall.com> wrote:
> So that's 12.8 c/s per bcrypt core for now. Given the current FPGA
> utilization with and without this one bcrypt core added, roughly how
> many such bcrypt cores would fit? What clock rate are you using?
> What's the maximum clock rate for this design on this device, as
> reported by ISE? Can you easily increase the clock rate to be closer to
> that maximum?
I'm travelling at the moment and my laptop battery doesn't work so I don't
have exact numbers, I'll have them in the evening.
What I remember is that synthesis report says maximum frequency is around
77 MHz when I create parallella bitstream. Howewer, when I generate
bitstream for zedboard without parallella, synthesis reports around 245
MHz. When I added bcrypt IP in parallella system I connected bus to FCLK0
which operates on 200 MHz and I use that clock in always @ (posedge clk) so
I think I can't go beyond that. There are 3 other clock pins but all of
them are less than 200 MHz. I think that one of them might be changed
without consequences for Epiphany.
Since simulation takes 7652913 clock cycles, clock rate being used is
around 100 MHz. I expected it to be 200 MHz since that is the frequency of
clock pin I connected to IP. Anyway, I'm pretty sure I remembered those
things correctly but as soon as I get home I'll check it to be sure.
Oh, and I made one mistake earlier. I said that latency of block RAM I'm
using is three cycles and it's actually two, I don't know why I counted
cycle in which I get data as latency. I'm sorry for inconvenience.
Katja
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