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Message-ID: <20130604024319.GA2204@openwall.com>
Date: Tue, 4 Jun 2013 06:43:19 +0400
From: Solar Designer <solar@...nwall.com>
To: john-dev@...ts.openwall.com
Subject: Re: FPGA reprogramming on ZedBoard / Parallella board
On Tue, Jun 04, 2013 at 06:20:37AM +0400, Solar Designer wrote:
> <solardiz> I've just extracted the bitstreams out of Parallella
> project's BOOT.BIN and ZedBoard's default SD card image BOOT.BIN with
> "dd" ...
>
> <solardiz> ... tried swapping the two on live Linux system - works
> like a charm. Here's where this turns out to be documented:
> http://www.xilinx.com/support/answers/46913.html
Here's what I did to obtain the two .bin format bitstreams for this test:
root@...aro-ubuntu-desktop:~# od -Ad -tx1 BOOT.BIN-zed | fgrep -1 '99 aa'
*
0000032 66 55 99 aa 58 4e 4c 58 00 00 00 00 00 00 01 01
0000048 c0 0a 00 00 2c 53 01 00 00 00 00 00 00 00 00 00
--
0089632 bb 00 00 00 44 00 22 11 ff ff ff ff ff ff ff ff
0089648 66 55 99 aa 00 00 00 20 01 20 02 30 00 00 00 00
0089664 01 00 02 30 00 00 00 00 01 80 00 30 00 00 00 00
^C
I took note of the offset of "ff ff ff ff 66 55 99 aa", then did:
dd if=BOOT.BIN-zed bs=89644 skip=1 of=bitstream-zed.bin
dd of=bitstream-zed.bin bs=4045564 count=0 seek=1
The second "dd" command is for truncation at the expected bitstream
length, which I found here:
http://forums.xilinx.com/t5/7-Series-FPGAs/Zynq-Z-7020-XC7Z020-Bitstream-Length/td-p/265640
Alexander
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