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Date: Mon, 30 May 2011 23:42:55 -0300
From: Yuri Gonzaga <>
Subject: Re: alternative approach

Hi, there.

I synthesized again the bflike.
Now, it is was to Spartan-6 xc6slx45, same device of pico e101.
I got the following results (This time I could generate a report with more

I could generate a schematic view as well (available on,
but is very big and dificult to track. I don't know if it will help.

No, I thought you'd show this partial carry addition bit-by-bit, without
> redundancy that you expect the synthesizer to detect and optimize out.
> But maybe this is not needed.  If we could see (and understand) a diagram
> of the generated circuit, we'd know for sure.  Or you can try both ways
> and compare the LUT counts.
> Oh, here's a simpler test: try replacing pcadd() with a simple addition
> or simple XOR.  If the synthesizer was smart enough, this should not
> change the LUT count.  If this does reduce the LUT count, then perhaps
> there was room for improvement.

I replaced pcadd() for simpler "a ^ b ^ mask" and it really reduced the LUT
However, I didn't figure out how to improve the pcadd() to do the right
thing using less LUTs.
All my attempts got wrong results in simulation.

Moreover, I am sending the verilog code again because the last one attached
has an error.




          Slice Logic Utilization             | Used | Available |

Number of Slice Registers                    35     54,576         1%

    Number used as Flip Flops                3
    Number used as Latches                 32

Number of Slice LUTs                        105     27,288         1%

    Number used as logic                    105     27,288         1%

        Number using O6 output only      91
        Number using O5 and O6           14
Number of occupied Slices                 32       6,822         1%

Number of LUT Flip Flop pairs used      109

    Number with an unused Flip Flop      75       109         68%
    Number with an unused LUT             4        109          3%
    Number of fully used LUT-FF pairs    30       109         27%
    Number of unique control sets            2
    Number of slice register sites lost      5     54,576         1%
    to control set restrictions

Number of bonded IOBs                       14       316          4%

Number of BUFG/BUFGMUXs               2        16         12%

    Number used as BUFGs                   2

Maximum Frequency: 76.940MHz

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