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Message-Id: <fbba3104-b67f-4c7b-a9db-a7d9773b83dc@app.fastmail.com>
Date: Sat, 21 Mar 2026 20:33:16 +0100
From: Alex Rønne Petersen <alex@...xrp.com>
To: "Rich Felker" <dalias@...c.org>
Cc: musl@...ts.openwall.com
Subject: Re: [PATCH] riscv: don't define fenv macros for soft float
On Sat, Mar 21, 2026, at 20:16, Rich Felker wrote:
> On Fri, Mar 20, 2026 at 06:52:34PM +0100, Alex Rønne Petersen wrote:
>> On Fri, Mar 20, 2026, at 18:49, Rich Felker wrote:
>> > On Fri, Jan 16, 2026 at 01:57:40PM +0100, Alex Rønne Petersen wrote:
>> >> As is done for all other soft float ports.
>> >> ---
>> >> arch/riscv32/bits/fenv.h | 5 +++++
>> >> arch/riscv64/bits/fenv.h | 5 +++++
>> >> 2 files changed, 10 insertions(+)
>> >>
>> >> diff --git a/arch/riscv32/bits/fenv.h b/arch/riscv32/bits/fenv.h
>> >> index 806ec40f..2c126e6b 100644
>> >> --- a/arch/riscv32/bits/fenv.h
>> >> +++ b/arch/riscv32/bits/fenv.h
>> >> @@ -1,3 +1,7 @@
>> >> +#ifdef __riscv_float_abi_soft
>> >> +#define FE_ALL_EXCEPT 0
>> >> +#define FE_TONEAREST 0
>> >> +#else
>> >> #define FE_INVALID 16
>> >> #define FE_DIVBYZERO 8
>> >> #define FE_OVERFLOW 4
>> >> @@ -10,6 +14,7 @@
>> >> #define FE_DOWNWARD 2
>> >> #define FE_UPWARD 3
>> >> #define FE_TOWARDZERO 1
>> >> +#endif
>> >>
>> >> typedef unsigned int fexcept_t;
>> >> typedef unsigned int fenv_t;
>> >> diff --git a/arch/riscv64/bits/fenv.h b/arch/riscv64/bits/fenv.h
>> >> index 806ec40f..2c126e6b 100644
>> >> --- a/arch/riscv64/bits/fenv.h
>> >> +++ b/arch/riscv64/bits/fenv.h
>> >> @@ -1,3 +1,7 @@
>> >> +#ifdef __riscv_float_abi_soft
>> >> +#define FE_ALL_EXCEPT 0
>> >> +#define FE_TONEAREST 0
>> >> +#else
>> >> #define FE_INVALID 16
>> >> #define FE_DIVBYZERO 8
>> >> #define FE_OVERFLOW 4
>> >> @@ -10,6 +14,7 @@
>> >> #define FE_DOWNWARD 2
>> >> #define FE_UPWARD 3
>> >> #define FE_TOWARDZERO 1
>> >> +#endif
>> >>
>> >> typedef unsigned int fexcept_t;
>> >> typedef unsigned int fenv_t;
>> >> --
>> >> 2.51.0
>> >
>> > I want to merge this but I noticed a possible inconsistency in how
>> > hard/soft fenv is handled. Here (and sjlj) use __riscv_float_abi_soft
>> > but fenv[-sf].[cS] use __riscv_flen. I think the latter are wrong
>> > since a softfloat ABI with hardfloat registers available should still
>> > be using the stub versions of fenv. But I want to make sure I'm
>> > interpreting the macros right.
>>
>> I agree with your interpretation. I missed that when writing the patch.
>
> Does the attached look ok to go with it?
LGTM
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