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Message-ID: <20250414145948.GA288056@port70.net>
Date: Mon, 14 Apr 2025 16:59:48 +0200
From: Szabolcs Nagy <nsz@...t70.net>
To: Alex Rønne Petersen <alex@...xrp.com>
Cc: musl@...ts.openwall.com
Subject: Re: [PATCH] clone: align the given stack pointer on or1k and
riscv
* Alex Rønne Petersen <alex@...xrp.com> [2025-02-08 05:39:59 +0100]:
> This is done for all(?) other musl ports, and is also done by glibc, and thus
> looks like an oversight for these ports. We ran into stack alignment issues for
> non-main threads in Zig as a result.
fwiw this patch looks good.
> ---
> src/thread/or1k/clone.s | 2 ++
> src/thread/riscv32/clone.s | 1 +
> src/thread/riscv64/clone.s | 1 +
> 3 files changed, 4 insertions(+)
>
> diff --git a/src/thread/or1k/clone.s b/src/thread/or1k/clone.s
> index 2473ac20..9a84aeba 100644
> --- a/src/thread/or1k/clone.s
> +++ b/src/thread/or1k/clone.s
> @@ -6,6 +6,8 @@
> .hidden __clone
> .type __clone,@function
> __clone:
> + l.xori r11, r0, -4
> + l.and r4, r4, r11
> l.addi r4, r4, -8
> l.sw 0(r4), r3
> l.sw 4(r4), r6
> diff --git a/src/thread/riscv32/clone.s b/src/thread/riscv32/clone.s
> index 3102239d..e2116e33 100644
> --- a/src/thread/riscv32/clone.s
> +++ b/src/thread/riscv32/clone.s
> @@ -8,6 +8,7 @@
> .type __clone, %function
> __clone:
> # Save func and arg to stack
> + andi a1, a1, -16
> addi a1, a1, -16
> sw a0, 0(a1)
> sw a3, 4(a1)
> diff --git a/src/thread/riscv64/clone.s b/src/thread/riscv64/clone.s
> index db908248..0e6f41a8 100644
> --- a/src/thread/riscv64/clone.s
> +++ b/src/thread/riscv64/clone.s
> @@ -8,6 +8,7 @@
> .type __clone, %function
> __clone:
> # Save func and arg to stack
> + andi a1, a1, -16
> addi a1, a1, -16
> sd a0, 0(a1)
> sd a3, 8(a1)
> --
> 2.43.0
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