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Message-ID: <20240227032929.GJ4163@brightrain.aerifal.cx>
Date: Mon, 26 Feb 2024 22:29:29 -0500
From: Rich Felker <dalias@...c.org>
To: Khem Raj <raj.khem@...il.com>
Cc: musl@...ts.openwall.com,
"Venkata Ramanaiah Nalamothu (QUIC)" <quic_vnalamot@...cinc.com>,
Stefan O'Rear <sorear@...tmail.com>
Subject: Re: RISC-V 32bit port in MUSL upstream
On Sun, Feb 25, 2024 at 10:17:32PM -0800, Khem Raj wrote:
> Thanks, I will test the patches on top of master this week and let you know
Thanks! I'm looking at the rebased patches and have some comments on
them. For the IPC one (attached here for reference), the time64 stuff
isn't so much for the sake of a legacy time32 ABI (which riscv32
doesn't have), although it does facilitate that too on archs that need
it. It's because the kernel is unable to give natively time64 ipc
structures, and needs translation. In the absence of a legacy ABI to
support, we could do translation that clobbers the same memory the
kernel put the split 32-bit fields in, but it's not aligned so there's
no easy way to do that, and just doing the same thing all other archs
do and having it at the end seems best.
Rich
> On Sun, Feb 25, 2024 at 6:16 PM Rich Felker <dalias@...c.org> wrote:
> >
> > On Wed, Nov 08, 2023 at 03:00:09PM +0000, Venkata Ramanaiah Nalamothu (QUIC) wrote:
> > > Ping.
> >
> > I believe this is actually close to ready-to-merge. I just pushed what
> > I think was the last missing prerequisite patch:
> >
> > https://git.musl-libc.org/cgit/musl/commit/?id=19563e1850808af216b1b84263bb7e83cccce506
> >
> > If the riscv32 port builds and works cleanly now with no further
> > changes to non-arch-specific code, I think it can be upstreamed now.
> > I'll try to take a look at this in the next couple days.
> >
> > Rich
> >
> >
> > > -----Original Message-----
> > > From: Venkata Ramanaiah Nalamothu (QUIC)
> > > Sent: Thursday, October 5, 2023 8:54 AM
> > > To: musl@...ts.openwall.com
> > > Subject: RE: [musl] RISC-V 32bit port in MUSL upstream
> > >
> > > Looks like that has changed and the ABI is being considered stable, otherwise GLIBC upstream wouldn't have accepted the RISC-V 32bit port, which is available since 2021 in GLIBC upstream.
> > > As per [1],
> > > * Support for the RISC-V ISA running on Linux has been expanded to run on 32-bit hardware. This is supported for the following ISA and ABI pairs:
> > > - rv32imac ilp32
> > > - rv32imafdc ilp32
> > > - rv32imafdc ilp32d
> > > The 32-bit RISC-V port requires at least Linux 5.4, GCC 7.1 and binutils 2.28.
> > >
> > > Regards,
> > > Ram Nalamothu
> > >
> > > [1] https://sourceware.org/pipermail/libc-alpha/2021-February/122207.html
> > >
> > > P.S: Apologies for the repost, the previous response was confusing because of the incorrect formatting.
> > >
> > > -----Original Message-----
> > > From: Markus Wichmann <nullplan@....net>
> > > Sent: Friday, September 29, 2023 8:13 PM
> > > To: musl@...ts.openwall.com
> > > Subject: Re: [musl] RISC-V 32bit port in MUSL upstream
> > >
> > > WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.
> > >
> > > Am Thu, Sep 28, 2023 at 04:39:37AM +0000 schrieb Venkata Ramanaiah Nalamothu (QUIC):
> > > > Thank you very much for sharing the patch set/development branch.
> > > >
> > > > Looking at your github tree commit history, it seems the tree is actively maintained.
> > > > May I know what is stopping from pushing these changes into MUSL community version?
> > > > Were there any technical challenges or someone just need to find time to work with the community to get the changes reviewed/merged?
> > >
> > > According to [0], main issue for Rich was that it was not a stable ABI yet back in 2020. Has that changed yet?
> > >
> > > Ciao,
> > > Markus
> > >
> > > [0] https://www.openwall.com/lists/musl/2020/03/12/2
View attachment "0007-Add-msg-sem-shm-structs-and-other-missing-defines.patch" of type "text/plain" (5053 bytes)
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