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Message-Id: <7BADA64C-F60D-49AC-9FCF-EF647B385208@gmail.com>
Date: Mon, 22 Jan 2024 12:38:30 +0900
From: Tatsuyuki Ishi <ishitatsuyuki@...il.com>
To: Fangrui Song <i@...kray.me>
Cc: musl@...ts.openwall.com
Subject: Re: Draft riscv64 TLSDESC implementation
> On Jan 22, 2024, at 8:48, Fangrui Song <i@...kray.me> wrote:
>
> On Sun, Jan 21, 2024 at 2:28 PM Rich Felker <dalias@...c.org> wrote:
>>
>> On Tue, Aug 22, 2023 at 01:38:21PM -0400, Rich Felker wrote:
>>> The psABI work is not finalized, but based on the current status of
>>> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373, I think
>>> the attached is a valid (but untested) implementation of TLSDESC for
>>> riscv64. Actually activating it requires also adding the relocation
>>> type macro to riscv64/reloc.h.
>>>
>>> If any rv folks could look it over and make sure I haven't made any
>>> stupid asm errors or missed any obvious optimizations, that would help
>>> to quickly get this merged when the psABI is finalized.
>>>
>>> Rich
>>
>>> .text
>>> .global __tlsdesc_static
>>> .hidden __tlsdesc_static
>>> .type __tlsdesc_static,%function
>>> __tlsdesc_static:
>>> ld a0,8(a0)
>>> jr t0
>>>
>>> .global __tlsdesc_dynamic
>>> .hidden __tlsdesc_dynamic
>>> .type __tlsdesc_dynamic,%function
>>> __tlsdesc_dynamic:
>>> add sp,sp,-8
>>> sd t1,(sp)
>>> sd t2,8(sp)
>>>
>>> ld t2,-8(tp) # t2=dtv
>>>
>>> ld a0,8(a0) # a0=&{modidx,off}
>>> ld t1,8(a0) # t1=off
>>> ld a0,(a0) # a0=modidx
>>> sll a0,a0,3 # a0=8*modidx
>>>
>>> add a0,a0,t2 # a0=dtv+8*modidx
>>> ld a0,(a0) # a0=dtv[modidx]
>>> add a0,a0,t1 # a0=dtv[modidx]+off
>>> sub a0,a0,tp # a0=dtv[modidx]+off-tp
>>>
>>> ld t1,(sp)
>>> ld t2,8(sp)
>>> add sp,sp,8
>>> jr t0
>>
>> Any feedback on this? Offhand, it looks like adjusting sp by 8 is
>> wrong and that should be 16. Anything else? Does anyone have recent
>> enough tooling to test this?
>
> Tatsuyuki, do you have links to the latest version of
> gcc/binutils/glibc patches?
The latest revisions are at [1,2,3]. I have plans to do a revision on binutils for more tests, and glibc for supporting saving vector registers, but I’m occupied with other priorities until the end of January.
> Downloading patches from these mailing lists is probably a large
> hurdle for many users, so having the relevant repositories online may
> help.
I’ll also link my GitHub repositories containing the same code at [4,5,6]. Right now they have some WIP commits (planned for sending in newer revisions) added on top, but they should still work fine.
[1]: https://inbox.sourceware.org/binutils/20231128085109.28422-1-ishitatsuyuki@gmail.com/
[2]: https://inbox.sourceware.org/libc-alpha/20230914084033.222120-1-ishitatsuyuki@gmail.com/
[3]: https://inbox.sourceware.org/gcc-patches/20231205070152.38360-1-ishitatsuyuki@gmail.com/
[4]: https://github.com/ishitatsuyuki/binutils/tree/rv-tlsdesc
[5]: https://github.com/ishitatsuyuki/glibc/tree/rv-tlsdesc/
[6]: https://github.com/ishitatsuyuki/gcc/tree/rv-tlsdesc/
Tatsuyuki.
> mold has implemented RISC-V TLSDESC.
>
> On the LLVM side, I have reviewed
> https://github.com/llvm/llvm-project/pull/66915 and am waiting for it
> to land, before I can check the lld status.
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