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Message-ID: <4559c029-6f1f-dd1c-3fb4-ae5b5c21eb31@esi.com.au>
Date: Sat, 21 Oct 2023 12:06:15 +1100 (AEDT)
From: Damian McGuckin <damianm@....com.au>
To: musl@...ts.openwall.com
Subject: Re: Floating Point Operations Cycles/Latency for ARM + RISC-V
+ POWER10
On Fri, 20 Oct 2023, David Edelsohn wrote:
> Have you looked at the scheduler description for ARM, RISC-V and POWER in
> GCC or LLVM?
No.
Thanks for the pointer - Damian
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