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Message-ID: <20230411125724.GL3630668@port70.net>
Date: Tue, 11 Apr 2023 14:57:24 +0200
From: Szabolcs Nagy <nsz@...t70.net>
To: Rich Felker <dalias@...c.org>
Cc: 张飞 <zhangfei@...iscas.ac.cn>,
"A. Wilcox" <awilfox@...lielinux.org>, musl@...ts.openwall.com
Subject: Re: [PATCH]Implementation of strlen function in riscv64
architecture
* Rich Felker <dalias@...c.org> [2023-03-22 08:15:30 -0400]:
> Regarding the code submitted for review, I'm pretty sure it's buggy
> because it doesn't seem to do anything with alignment. If you pass it
> a pointer to the last byte of a page whose contents are zero, it will
> attempt to load the rest of the vector from the next page, and fault.
the aarch64 sve isa extension has 'first faulting register' mask
and there are load/store instructions that set it instead of
actually faulting when a vector goes off at the end of a page.
i suspect riscv copied this piece of architecture (as well as the
variable vector length).
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