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Message-ID: <20211207005940.GK7074@brightrain.aerifal.cx>
Date: Mon, 6 Dec 2021 19:59:41 -0500
From: Rich Felker <dalias@...c.org>
To: Florian Weimer <fweimer@...hat.com>
Cc: Stijn Tintel <stijn@...ux-ipv6.be>, musl@...ts.openwall.com
Subject: Re: [PATCH] ppc64: check for AltiVec in setjmp/longjmp
On Tue, Dec 07, 2021 at 01:37:12AM +0100, Florian Weimer wrote:
> * Stijn Tintel:
>
> > diff --git a/src/setjmp/powerpc64/setjmp.s b/src/setjmp/powerpc64/setjmp.s
> > index 37683fda..32853693 100644
> > --- a/src/setjmp/powerpc64/setjmp.s
> > +++ b/src/setjmp/powerpc64/setjmp.s
> > @@ -69,7 +69,17 @@ __setjmp_toc:
> > stfd 30, 38*8(3)
> > stfd 31, 39*8(3)
> >
> > - # 5) store vector registers v20-v31
> > + # 5) store vector registers v20-v31 if hardware supports AltiVec
> > + mflr 0
> > + bl 1f
> > + .hidden __hwcap
> > + .long __hwcap-.
> > +1: mflr 4
>
> This de-balances the return stack and probably has quite severe
> performance impact. The ISA manual says to use
>
> bcl 20,31,$+4
>
> and you'll have to store the __hwcap offset somewhere else.
To begin with, let's change the .s files to .S files and put the whole
branch logic inside #ifndef __ALTIVEC__ so that it does not impact
normal builds with an ISA level where Altivec can be assumed to be
present.
I'm not sufficiently familiar with the PowerPC ISA to know how bcl
works, but if there's a less expensive solution along those lines
that's compatible with all ISA levels, by all means let's use it. The
same could be done for powerpc-sf (32-bit) and its SPE branches, too.
Also the add and lwz can be used into lwzx (indexed load).
Rich
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