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Message-ID: <CAGWvnymXg_Cv_7-TXQFPg5JTTWLYX_qsweg0ZFOYuG8dms7eSQ@mail.gmail.com>
Date: Tue, 7 Dec 2021 13:57:11 -0500
From: David Edelsohn <dje.gcc@...il.com>
To: musl@...ts.openwall.com
Subject: Re: [PATCH] ppc64: check for AltiVec in setjmp/longjmp
On Tue, Dec 7, 2021 at 1:39 PM Markus Wichmann <nullplan@....net> wrote:
>
> On Tue, Dec 07, 2021 at 08:25:09AM -0500, Rich Felker wrote:
> > On Mon, Dec 06, 2021 at 08:44:47PM -0500, David Edelsohn wrote:
> > > It should work, but it's slightly preferred to use $+4 because one
> > > explicitly wants the address of the next instruction and labels of the
> >
> > In this case we don't want the address of the next instruction. We
> > want the address of the constant __hwcap-.
> >
> > Rich
>
> According to at least one source I found at some point (and can't seem
> to find right away), "bcl 20,31,+4" is the one special form of the
> instruction that is most likely to circumvent the shadow stack. I have
> seen "bcl 20,31,label" in the wild, even in cases where the label didn't
> directly follow the instruction, so maybe it works, maybe it doesn't.
>
> That said, architecturally it will work either way. We are only talking
> about an implementation detail, and both IBM's and Freescale's/NXP's
> documentation is very cagey about revealing any of those. The
> instruction is specified to exist and do the right thing (namely to
> branch with linking unconditionally) all the way back to the first
> PowerPC implementations from the early nineties, but whether such a
> thing as a branch predictor even exists, or if it uses shadow stacks to
> predict the "blr" target, is entirely unspecified.
>
> So yeah, you might want to restructure the code to move the hwcap offset
> somewhere else.
Only "$+4" is documented. As you wote, it probably would be best to
place the offset somewhere else. It also is not good practice to have
arbitrary bit patterns of data that potentially are not valid
instructions in the instruction stream.
Thanks, David
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