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Message-ID: <20211019141622.GN7074@brightrain.aerifal.cx>
Date: Tue, 19 Oct 2021 10:16:24 -0400
From: Rich Felker <dalias@...c.org>
To: Arnd Bergmann <arnd@...db.de>
Cc: musl@...ts.openwall.com, Takashi Iwai <tiwai@...e.de>,
Michael Forney <mforney@...rney.org>,
ALSA Development Mailing List <alsa-devel@...a-project.org>,
Takashi Iwai <tiwai@...e.com>, Baolin Wang <baolin.wang@...aro.org>,
y2038 Mailman List <y2038@...ts.linaro.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Mark Brown <broonie@...nel.org>,
Baolin Wang <baolin.wang7@...il.com>
Subject: Re: Re: [alsa-devel] [PATCH v7 8/9] ALSA: add new 32-bit
layout for snd_pcm_mmap_status/control
On Mon, Oct 18, 2021 at 04:42:04PM -0400, Rich Felker wrote:
> On Mon, Oct 18, 2021 at 05:26:35PM +0200, Arnd Bergmann wrote:
> > On Mon, Oct 18, 2021 at 5:08 PM Rich Felker <dalias@...c.org> wrote:
> > > On Mon, Oct 18, 2021 at 04:58:03PM +0200, Takashi Iwai wrote:
> > > > On Mon, 18 Oct 2021 16:43:00 +0200, Rich Felker wrote:
> > >
> > > No, I don't think so. The musl translator is to translate between the
> > > time64 ioctl structures and the old time32 ones for the sake of
> > > executing on an old kernel. Up til now, it has been broken comparably
> > > to how 32-bit binaries running in compat mode on a 64-bit kernel were
> > > broken: the code in musl translated the time64 structure to (and back
> > > from) the time32 one assuming the intended padding. But the
> > > application was using the actual kernel uapi struct where the padding
> > > was (and still is) illogical. Thus, nothing was built with the wrong
> > > ABI; it's only the musl-internal translation logic that was wrong (and
> > > only pre-time64 kernels are affected).
> > >
> > > The attached patch should fix it, I think.
> > >
> > > + int adj = BYTE_ORDER==BIG_ENDIAN ? 4 : 0;
> > > + if (dir==W) {
> > > + memcpy(old+68, new+72+adj, 4);
> > > + memcpy(old+72, new+72+4+2*adj, 4);
> >
> > I think that should be "new+72+4+3*adj": the "2*adj" would
> > be what the code does already for the originally intended
> > format.
>
> Well for little endian either would work (because adj is 0 :) but yes
> there are 3 such paddings before the second member on big endian, so
> it should be 3.
How about this? It avoids open coding the logic and handles it as 2
4-byte substructures with endian-specific offsets.
Rich
View attachment "snd_pcm_mmap_control_v2.diff" of type "text/plain" (1507 bytes)
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