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Message-ID: <20200401061825.GA6733@APC301.andestech.com>
Date: Wed, 1 Apr 2020 14:18:27 +0800
From: Ruinland ChuanTzu Tsai <ruinland@...estech.com>
To: <musl@...ts.openwall.com>
CC: <alankao@...estech.com>, <imruinland.cs00@...nctu.edu.tw>
Subject: About "stable ABI" for riscv32 kernel issue and Alpine port
Hi Rich and All,
Back in 13th Mar, Rich has stated that "kernel has not declared it
(RV32 Linux) a stable ABI yet." I'm wondering whether Rich could kindly
elaborate a little bit more details about this concern ?
Since my employer, Andes Tech, is one of the founding plantium memeber
of RISC-V Foundation and we're shipping a considerable amount of
Linux-running RV32 products at the time we're speaking, we will be
happy to help on the kernel side and make it more stablized and secured.
During my pastime, I've ported Alpine Linux with musl 1.2.0 to a
publicily available and open-sourced platform, LiteX/VexRiscv[1], which
could be synthesized and "burnt" to a Lattice ECP5-5G Versa Evaluation
Board with completely FOSS toolchain without any closed source
component. [2]
And here's the footage of booting :
https://asciinema.org/a/315205
Unfortunately, since my musl 1.2.0 is an inhouse work and we are still
polishing and preparing it for upstreaming, please excuse me from not
releasing the cpio image and stuffs at this time being.
P.S.
Regarding the last mail:
https://www.openwall.com/lists/musl/2020/03/13/4
I'm not really qualified to answer the reason/profit of lacking LR/SC
pair. Yet just a rough hunch that LR/SC is much stronger in atomicity
than other AMOs.
Best regards and looking forward to the prosperity,
Ruinland ChuanTzu Tsai
[1] https://github.com/litex-hub/linux-on-litex-vexriscv
[2] https://symbiflow.github.io/
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