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Message-ID: <20200313021318.GL11469@brightrain.aerifal.cx>
Date: Thu, 12 Mar 2020 22:13:18 -0400
From: Rich Felker <dalias@...c.org>
To: musl@...ts.openwall.com
Subject: Re: 答复: musl support
riscv32
On Fri, Mar 13, 2020 at 02:05:09AM +0000, chengzhiwei (C) wrote:
> Thanks, Hopefully I am!
>
> Another thing is about atomic operation(if 32-bit based on what's
> upstram in musl for riscv64), musl's atomic operation for riscv64 is
> a handwritten assembly version, but some RISCV-V MCU omit such
> instructions LR/SC specified in the A standard extension. Someone do
> related work to support processors without atomic instructions? Or
> considering the possibility of implementing the functionality in C
> code.
If the hardware lacks them the kernel needs to trap and emulate, or
provide some other mechanism (like kuser_helper on old ARM). There's
no way to have a working implementation without compare-and-swap.
I've said many times that it's ridiculous that RISC-V made them
optional. For a single-core CPU LR/SC are trivial to implement. LR
just sets a flag and all interrupts clear the flag. SC stores only if
the flag is set.
Rich
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