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Message-ID: <20190927003821.GE9017@brightrain.aerifal.cx>
Date: Thu, 26 Sep 2019 20:38:21 -0400
From: Rich Felker <dalias@...c.org>
To: musl@...ts.openwall.com
Subject: Re: mips fp32/fpxx/fp64 issues, r6 sjlj broken
On Thu, Sep 26, 2019 at 07:23:50PM -0400, Rich Felker wrote:
> On Thu, Sep 26, 2019 at 06:45:21PM -0400, Rich Felker wrote:
> > Also, mipsr6 (the new mips-family ISA that's not compatible with
> > previous mips) always uses the 64-bit register mode. We presently do
> > not have setjmp/longjmp code that works with this case at all
> > (existing code will wrongly save low 32-bits of 2 registers instead of
> > single whole double register); somehow nobody has noticed that this is
> > broken. Making this conditional on __mips_isa_rev >= 6 should not be
> > hard.
>
> Attached patch should work, but maybe isn't the best thing to do. I
> think using sdc1/ldc1 and just even indices like on r6 would also be
> valid for pre-r6 mips using fp32 or fpxx abi; with FR=0, it would
> save/restore the pair of 32-bit registers, and with FR=1, fp32 code
> could not be running anyway, and fpxx code should work fine. However,
> mips I lacks the ldc1/stc1 instructions, so at the very least we'd
> need to leave the old form in place for mips I. Or maybe use the s.d
> and l.d mnemonics that automatically assemble to the right choice
> based on the isa level...
Two new versions of the patch. I think I prefer the last one.
l.d and s.d expand to pairs of lwc1 and swc1 on mips1, and otherwise
expand to ldc1 and sdc1. ldc1 and sdc1 in turn behave just like pairs
of lwc1 and swc1 when FR=0, but additionally match the fpxx ABI when
FR=1.
With this the r6 and clang issues should be fixed.
Rich
View attachment "mips-sjlj-2.diff" of type "text/plain" (1200 bytes)
View attachment "mips-sjlj-3.diff" of type "text/plain" (1398 bytes)
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