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Message-ID: <20190517160125.pg4ugmzq66ciqi6r@gmail.com>
Date: Sat, 18 May 2019 00:01:25 +0800
From: Fangrui Song <i@...kray.me>
To: musl@...ts.openwall.com
Subject: Re: [PATCH] fix tls offsets when p_vaddr%p_align != 0 for
TLS_ABOVE_TP
On 2019-05-17, Szabolcs Nagy wrote:
>* Rich Felker <dalias@...c.org> [2019-05-16 21:50:43 -0400]:
>> On Fri, May 17, 2019 at 12:51:18AM +0200, Szabolcs Nagy wrote:
>> > + p->tls.offset = tls_offset + ( (p->tls_align-1) &
>> ~~~~~~~~~
>>
>> This should be tls.align. I can fix it up though when applying.
>
>yes, my bad.
I have verified 0001-fix-tls-offsets-when-p_vaddr-p_align-0-for-TLS_ABOVE.patch
With the following lld patch, p_vaddr%p_align!=0, the reproduce program
in https://bugs.llvm.org/show_bug.cgi?id=41527 works.
(a local exec variable defined in executable accessed by another module via `extern __thread int a` (initial exec/generic dynamic))
diff --git i/ELF/InputSection.cpp w/ELF/InputSection.cpp
index 1bf67e2a3..ff365ef0c 100644
--- i/ELF/InputSection.cpp
+++ w/ELF/InputSection.cpp
@@ -594,7 +594,8 @@ static int64_t getTlsTpOffset() {
// NB: While the ARM/AArch64 ABI formally has a 2-word TCB size, lld
// effectively increases the TCB size to 8 words for Android compatibility.
// It accomplishes this by increasing the segment's alignment.
- return alignTo(Config->Wordsize * 2, Out::TlsPhdr->p_align);
+ return alignTo(Config->Wordsize * 2, Out::TlsPhdr->p_align,
+ Out::TlsPhdr->FirstSec->Addr);
case EM_386:
case EM_X86_64:
// Variant 2. The TLS segment is located just before the thread pointer.
(I hope someone can improve my qemu workflow:
qemu-system-aarch64 -M virt -cpu cortex-a57 -nographic -smp 1 -m 2048 -kernel vmlinuz-vanilla -initrd initramfs-vanilla -append "console=ttyAMA0 ip=dhcp alpine_repo=http://dl-cdn.alpinelinux.org/alpine/edge/main")
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