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Message-ID: <20181025195057.GP5150@brightrain.aerifal.cx>
Date: Thu, 25 Oct 2018 15:50:57 -0400
From: Rich Felker <dalias@...c.org>
To: musl@...ts.openwall.com
Subject: Re: [PATCH] PPC64 IEEE128 bit FP support
On Thu, Oct 25, 2018 at 03:12:51PM -0400, David Edelsohn wrote:
> The IBM Power9 processor adds support for IEEE 754 quad precision 128
> binary floating point. The attached patch from my colleague should
> enable the basic support. musl never has supported the IBM long
> double floating point format. The patch only enables musl long double
> support when built with and used with a toolchain that enables IEEE
> 128 bit FP.
>
> Any suggestions on how to transition this support in musl?
>
> Thanks, David
>
> P.S. A Power9 system now is available in the GNU Compile Farm.
> From de28b4d36616ed583ec247639d13bd76216fd3bf Mon Sep 17 00:00:00 2001
> From: Tulio Magno Quites Machado Filho <tuliom@...ux.ibm.com>
> Date: Fri, 19 Oct 2018 10:09:49 -0300
> Subject: [PATCH] powerpc64: Add support for IEEE 128-bit floating point long
> double
>
> ---
> INSTALL | 4 ++--
> arch/powerpc64/bits/float.h | 17 +++++++++++++++++
> 2 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/INSTALL b/INSTALL
> index a2a142bf..00d7282d 100644
> --- a/INSTALL
> +++ b/INSTALL
> @@ -76,8 +76,8 @@ and ABI combinations:
>
> * PowerPC64
> * Both little and big endian variants are supported
> - * Compiler toolchain must provide 64-bit long double, not IBM
> - double-double or IEEE quad
> + * Compiler toolchain must provide 64-bit long double, or IEEE 128-bit
> + long double not IBM double-double
> * Compiler toolchain must use the new (ELFv2) ABI regardless of
> whether it is for little or big endian
>
> diff --git a/arch/powerpc64/bits/float.h b/arch/powerpc64/bits/float.h
> index c4a655e7..4e485512 100644
> --- a/arch/powerpc64/bits/float.h
> +++ b/arch/powerpc64/bits/float.h
> @@ -1,3 +1,19 @@
> +#if __LDBL_MANT_DIG__ == 113
> +#define LDBL_TRUE_MIN 6.47517511943802511092443895822764655e-4966L
> +#define LDBL_MIN 3.36210314311209350626267781732175260e-4932L
> +#define LDBL_MAX 1.18973149535723176508575932662800702e+4932L
> +#define LDBL_EPSILON 1.92592994438723585305597794258492732e-34L
> +
> +#define LDBL_MANT_DIG 113
> +#define LDBL_MIN_EXP (-16381)
> +#define LDBL_MAX_EXP 16384
> +
> +#define LDBL_DIG 33
> +#define LDBL_MIN_10_EXP (-4931)
> +#define LDBL_MAX_10_EXP 4932
> +
> +#define DECIMAL_DIG__ 36
> +#else
> #define FLT_EVAL_METHOD 0
>
> #define LDBL_TRUE_MIN 4.94065645841246544177e-324L
> @@ -14,3 +30,4 @@
> #define LDBL_MAX_10_EXP 308
>
> #define DECIMAL_DIG 17
> +#endif
> --
> 2.14.4
This patch can't be applied without corresponding patches to configure
and arch/powerpc64/reloc.h that define a new ldso name for the ABI.
Otherwise it produces ABI breakage.
As submitted, it also seems to be removing FLT_EVAL_METHOD in the new
ABI, but this is easily fixed.
Also, what is the calling convention for IEEE quad? Does it use
registers that are only available on certain models, so that not just
the hard-float code using it, but also the basic ABI, has a minimum
ISA level associated with it? Or is the calling convention compatible
with older models too and just needing softfloat code on them (which
libgcc presumably provides)?
Rich
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