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Message-ID: <20180928024749.GS17995@brightrain.aerifal.cx>
Date: Thu, 27 Sep 2018 22:47:49 -0400
From: Rich Felker <dalias@...c.org>
To: musl@...ts.openwall.com
Subject: Re: riscv port for review
On Thu, Sep 27, 2018 at 10:24:04PM -0400, Rich Felker wrote:
> Pulled from here:
> https://github.com/riscv/riscv-musl/commit/6a4f4a9c774608add4b02f95322518bd2f5f51ee
>
> Attached for review.
> diff --git a/arch/riscv32/bits/alltypes.h.in b/arch/riscv32/bits/alltypes.h.in
> new file mode 100644
> index 0000000..66ca18a
> --- /dev/null
> +++ b/arch/riscv32/bits/alltypes.h.in
> @@ -0,0 +1,26 @@
> +#define _Addr int
> +#define _Int64 long long
> +#define _Reg int
> +
> +TYPEDEF __builtin_va_list va_list;
> +TYPEDEF __builtin_va_list __isoc_va_list;
> +
> +#ifndef __cplusplus
> +TYPEDEF int wchar_t;
> +#endif
> +
> +TYPEDEF float float_t;
> +TYPEDEF double double_t;
> +
> +TYPEDEF struct { long long __ll; long double __ld; } max_align_t;
> +
> +TYPEDEF long time_t;
Is riscv32 time_t really 32-bit? If so that's really disappointing,
but presumably unfixable...
Rich
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