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Message-ID: <CA+RmVGzGDQOMVR3=m=RatUG_AjKQ0z=w4qaT53NyM5_048iNLg@mail.gmail.com>
Date: Sat, 26 May 2018 00:20:04 +0200
From: Phillip Berndt <phillip.berndt@...glemail.com>
To: musl@...ts.openwall.com
Subject: Re: TLS issue on aarch64
2018-05-25 16:50 GMT+02:00 Szabolcs Nagy <nsz@...t70.net>:
> i think the constraints for tp are:
>
> - tp must be aligned to 'tls_align'
>
> - tp must be at a small fixed offset from the end
> of pthread struct (so asm code can access the dtv)
>
> - tp + off must be usable memory for tls for off >= 16
> (this is aarch64 specific)
>
Hmm.. but these constraints do not explain the extra offset of one
alignment I'm seeing in the GCC output, do they? If I compile a
program with a single TLS variable with
__attribute__((aligned(n)) that does nothing but try to reference and
print said variable, I get the
following assembler code from GCC:
For n = 0x1000:
400194: d53bd041 mrs x1, tpidr_el0
400198: b0000040 adrp x0, 409000 <__subtf3+0xd18>
40019c: 91400421 add x1, x1, #0x1, lsl #12
4001a0: 91000021 add x1, x1, #0x0
For n = 0x100:
400194: d53bd041 mrs x1, tpidr_el0
400198: b0000040 adrp x0, 409000 <__subtf3+0xd18>
40019c: 91400021 add x1, x1, #0x0, lsl #12
4001a0: 91040021 add x1, x1, #0x100
For n = 0x10:
400194: d53bd041 mrs x1, tpidr_el0
400198: b0000040 adrp x0, 409000 <__subtf3+0xd18>
40019c: 91400021 add x1, x1, #0x0, lsl #12
4001a0: 91004021 add x1, x1, #0x10
That's how I came up with the mem += libc.tls_align hack in the first place.
- Phillip
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