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Message-ID: <20170421132650.GD17319@brightrain.aerifal.cx>
Date: Fri, 21 Apr 2017 09:26:50 -0400
From: Rich Felker <dalias@...c.org>
To: Jaydeep Patil <Jaydeep.Patil@...tec.com>
Cc: Andre McCurdy <armccurdy@...il.com>,
"musl@...ts.openwall.com" <musl@...ts.openwall.com>
Subject: Re: microMIPS32R2 O32 port
On Thu, Apr 13, 2017 at 04:29:10AM +0000, Jaydeep Patil wrote:
> Hi,
>
> With this branch (micromips32r2_v2) we are supporting microMIPS
> cores that co-exist with MIPS. The MUSL library must be built with
> -minterlink-compressed option as there are couple of hand-written
> MIPS only functions. For microMIPS only cores we will create a
> different subarch.
I don't think there's any indication yet that a different subarch is
appropriate for micromips-only cores. This would only be the case if
they are somehow ABI-incompatible with normal mips. If it would be
possible to run binaries that were built for micromips only on a cpu
core that supports both, using a libc.so that was built either for
plain mips or micromips or a mix, then for our purposes it's the same
arch, just a different ISA level/profile.
Rich
> >-----Original Message-----
> >From: Andre McCurdy [mailto:armccurdy@...il.com]
> >Sent: 13 April 2017 AM 03:17
> >To: musl@...ts.openwall.com
> >Cc: Jaydeep Patil
> >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port
> >
> >On Wed, Apr 12, 2017 at 1:27 PM, Rich Felker <dalias@...c.org> wrote:
> >> On Wed, Apr 12, 2017 at 09:25:35PM +0200, Szabolcs Nagy wrote:
> >>> * Jaydeep Patil <Jaydeep.Patil@...tec.com> [2017-04-12 11:54:10 +0000]:
> >>> > Hi Rich,
> >>> >
> >>> > We can reuse existing MIPS code for microMIPS. There are places where
> >we read from $ra must be compiled for MIPS.
> >>> > Please refer to https://github.com/JaydeepIMG/musl-
> >1/tree/micromips32r2_v2 for modifications.
> >>> >
> >>>
> >>> is micromips a different encoding for mips instructions that works on
> >>> some cpus but not others?
> >>
> >> Yes, it's something like thumb or thumb2 on arm, or the riscv
> >> compressed isa. What I'm not clear on is whether there are
> >> micromips-only cpu models that can't execute normal mips.
> >
> >According to:
> >
> > https://imagination-technologies-cloudfront-
> >assets.s3.amazonaws.com/documentation/MIPS_Architecture_microMIPS32
> >_InstructionSet_AFP_P_MD00582_06.04.pdf
> >
> >"microMIPS is also an alternative to the MIPS® instruction encoding and can
> >be implemented in parallel or stand-alone."
> >
> >"If only one ISA mode exists (either MIPS or microMIPS) then this mode
> >switch mechanism does not exist"
> >
> >> If so we probably need the ability to build musl as micromips, but as
> >> long as cpus which support both support interworking (calls between
> >> the two type of code in the same process) reasonably, I don't think
> >> there's any reason to consider it a different subarch.
> >>
> >> If not (that is, if all cpus that support micromips also support the
> >> normal mips isa) then I fail to see why there's any need to compile
> >> musl's asm files as micromips. They're not size or performance
> >> bottlenecks.
> >>
> >> Rich
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