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Message-ID: <CAGWvny=rbe+QHnrVNrQtNA7+q7H07HutQ7w2maoV+L5=3fpcbg@mail.gmail.com>
Date: Mon, 8 Feb 2016 18:52:55 -0500
From: David Edelsohn <dje.gcc@...il.com>
To: Rich Felker <dalias@...c.org>
Cc: musl@...ts.openwall.com
Subject: Re: Re: musl libc for PPC64
On Mon, Feb 8, 2016 at 6:29 PM, Rich Felker <dalias@...c.org> wrote:
> On Mon, Feb 08, 2016 at 06:24:27PM -0500, David Edelsohn wrote:
>> You *can* use v2 ABI for BE, but there is no software to run. There
>> is no software or ecosystem or operating system that runs v2 ABI BE.
>> It's not a hardware limitation, but there is no environment for the
>> alternate combination.
>
> Indeed. At this point there's no musl ecosystem for ppc64 at all
> though; whatever we add is a fresh start.
>
>> >> IBM has announced that the next generation of the processor will
>> >> support native IEEE128 floating point in hardware. There will be
>> >> software emulation for the current processors. Support is included in
>> >> the forthcoming GCC 6.
>> >
>> > OK. Does the existing software emulation properly update the hardware
>> > floating point status (exception flags) and use the rounding mode?
>>
>> I'm not sure what you mean. The software emulation assumes the
>> hardware support is not present. It doesn't mirror back the state to
>> the processor in 64 bit mode. But the emulation is fully IEEE128
>> compliant.
>
> if fesetround(FE_DOWNWARD) succeeds but then long double math still
> rounds to nearest, that's not IEEE compliant.
>
> The big obstacle to having fenv with softfloat on fully-softfloat
> archs is the lack of register state for the rounding mode and
> exception flags, so it should be possible to do this right as long as
> the cpu has status/mode registers for single/double, which the
> soft-quad code can then access/set. If this isn't done right already
> we could either try to get it fixed in libgcc or punt and go with
> ld64.
Who would be interested in working on this?
Thanks, David
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