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Message-ID: <CAH42g78VoupCzpKbGx3-TCNe_=y-BcQHi1iOV3w=5GkhTdyYjQ@mail.gmail.com>
Date: Thu, 26 Mar 2015 18:34:24 +1000
From: Roman Titov <titovroman@...il.com>
To: "musl@...ts.openwall.com" <musl@...ts.openwall.com>
Subject: Re: GSoC 2015. Porting musl libc to RISC-V project. Proposal
help and feedback.
2015-03-26 15:11 GMT+10:00 Rich Felker <dalias@...c.org>:
>
> Can you clarify the G suffix?
>
RISC-V ISA is modular.
Specification says that only base integer subset is mandatory.
At the moment there is RV32I or RV64I bases, and RV128I possible
somwhere in the future. Integer base bitness defines overall bitness
of resulting ISA, obviously.
Above integer base there is also a set of "standard extensions":
M - integer multiplication and division,
A - atomic instructions,
F - single-precision floating point,
D - double-precision floating point.
Direct quote from ISA spec (last sentence on page 4 continued on page 5):
"An integer base plus these four standard extensions (“IMAFD”) is
given the abbreviation “G” and provides a
general-purpose scalar instruction set. RV32G and RV64G are currently
the default target of our
compiler toolchains."
I think this also answers one of your next questions:
>
> This should not include anything except fenv on soft-float archs. I'm
> not clear on whether the proposed port is soft-float, hard-float, or
> both, and whether there would be separate ABIs for both or just one
> ABI.
>
G is a default target, so I think we also targeting it.
Regards,
Roman Titov
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