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Message-Id: <5AA8BF10-8987-4FCB-870C-667A5228D97B@gmail.com>
Date: Mon, 17 Jun 2019 09:53:54 -0700
From: Nadav Amit <nadav.amit@...il.com>
To: Andy Lutomirski <luto@...nel.org>
Cc: Dave Hansen <dave.hansen@...el.com>,
Alexander Graf <graf@...zon.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marius Hillenbrand <mhillenb@...zon.de>,
kvm list <kvm@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
Kernel Hardening <kernel-hardening@...ts.openwall.com>,
Linux-MM <linux-mm@...ck.org>,
Alexander Graf <graf@...zon.de>,
David Woodhouse <dwmw@...zon.co.uk>,
the arch/x86 maintainers <x86@...nel.org>,
Peter Zijlstra <peterz@...radead.org>
Subject: Re: [RFC 00/10] Process-local memory allocations for hiding KVM
secrets
> On Jun 17, 2019, at 9:14 AM, Andy Lutomirski <luto@...nel.org> wrote:
>
> On Mon, Jun 17, 2019 at 9:09 AM Dave Hansen <dave.hansen@...el.com> wrote:
>> On 6/17/19 8:54 AM, Andy Lutomirski wrote:
>>>>> Would that mean that with Meltdown affected CPUs we open speculation
>>>>> attacks against the mmlocal memory from KVM user space?
>>>> Not necessarily. There would likely be a _set_ of local PGDs. We could
>>>> still have pair of PTI PGDs just like we do know, they'd just be a local
>>>> PGD pair.
>>> Unfortunately, this would mean that we need to sync twice as many
>>> top-level entries when we context switch.
>>
>> Yeah, PTI sucks. :)
>>
>> For anyone following along at home, I'm going to go off into crazy
>> per-cpu-pgds speculation mode now... Feel free to stop reading now. :)
>>
>> But, I was thinking we could get away with not doing this on _every_
>> context switch at least. For instance, couldn't 'struct tlb_context'
>> have PGD pointer (or two with PTI) in addition to the TLB info? That
>> way we only do the copying when we change the context. Or does that tie
>> the implementation up too much with PCIDs?
>
> Hmm, that seems entirely reasonable. I think the nasty bit would be
> figuring out all the interactions with PV TLB flushing. PV TLB
> flushes already don't play so well with PCID tracking, and this will
> make it worse. We probably need to rewrite all that code regardless.
How is PCID (as you implemented) related to TLB flushing of kernel (not
user) PTEs? These kernel PTEs would be global, so they would be invalidated
from all the address-spaces using INVLPG, I presume. No?
Having said that, the fact that every hypervisor implements PV-TLB
completely differently might be unwarranted.
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