kernel-hardening - Re: [PATCH V5 0/5] KVM: X86: Introducing ROE Protection Kernel Hardening

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Message-ID: <CAAGnT3ao2YugWW_1TuZw4+OiLQsBYLXtcYjARagZ3pGwFhvGZg@mail.gmail.com>
Date: Thu, 1 Nov 2018 01:21:00 +0200
From: Ahmed Soliman <ahmedsoliman0x666@...il.com>
To: Igor Stoppa <igor.stoppa@...il.com>
Cc: Paolo Bonzini <pbonzini@...hat.com>, Radim Krčmář <rkrcmar@...hat.com>, 
	nathan Corbet <corbet@....net>, Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, 
	Borislav Petkov <bp@...en8.de>, "H. Peter Anvin" <hpa@...or.com>, "the arch/x86 maintainers" <x86@...nel.org>, kvm@...r.kernel.org, 
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	김인겸 <ovich00@...il.com>, 
	Kernel Hardening <kernel-hardening@...ts.openwall.com>, nigel.edwards@....com, 
	Boris Lukashev <blukashev@...pervictus.com>, Hossam Hassan <7ossam9063@...il.com>, 
	Ahmed Lotfy <A7med.lotfey@...il.com>, Mohamed Azab <mazab@...edu>
Subject: Re: [PATCH V5 0/5] KVM: X86: Introducing ROE Protection Kernel Hardening

Hello Igor,
> This is very interesting, because it seems a very good match to the work
> I'm doing, for supporting the creation of more targets for protection:
>
> https://www.openwall.com/lists/kernel-hardening/2018/10/23/3
>
> In my case the protection would extend also to write-rate type of data.
> There is an open problem of identifying legitimate write-rare
> operations, however it should be possible to provide at least a certain
> degree of confidence.

I have checked your patch set. In our work we were originally planning to do
something similar to write_rare just so we can differentiate between memory
chunks that may be modified and those that will be set once and never modify.
I see you are planning to do a white paper too, actually we are doing
an academic
paper based on our work. If you would like to collaborate, so that ROE
and write_rare
would integrate well from the beginning, we will be glad to do so.

Thanks,
--
Ahmed
Junior Researcher , IoT and Cyber Security lab, SmartCI , Alexandria
University, & CIS @  VMI

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