kernel-hardening - Re: [PATCHv3 11/11] arm64: docs: document pointer authentication

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Message-ID: <20180422090003.GA24344@amd>
Date: Sun, 22 Apr 2018 11:00:03 +0200
From: Pavel Machek <pavel@....cz>
To: Marc Zyngier <marc.zyngier@....com>
Cc: Mark Rutland <mark.rutland@....com>,
	linux-arm-kernel@...ts.infradead.org, arnd@...db.de,
	catalin.marinas@....com, cdall@...nel.org, drjones@...hat.com,
	kvmarm@...ts.cs.columbia.edu, linux-arch@...r.kernel.org,
	ramana.radhakrishnan@....com, suzuki.poulose@....com,
	will.deacon@....com, linux-kernel@...r.kernel.org,
	awallis@...eaurora.org, kernel-hardening@...ts.openwall.com
Subject: Re: [PATCHv3 11/11] arm64: docs: document pointer authentication

On Sun 2018-04-22 09:47:29, Marc Zyngier wrote:
> On Sun, 22 Apr 2018 09:05:21 +0100,
> Pavel Machek wrote:
> > 
> > Hi!
> > 
> > > @@ -205,6 +205,14 @@ Before jumping into the kernel, the following conditions must be met:
> > >      ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
> > >    - The DT or ACPI tables must describe a GICv2 interrupt controller.
> > >  
> > > +  For CPUs with pointer authentication functionality:
> > > +  - If EL3 is present:
> > > +    SCR_EL3.APK (bit 16) must be initialised to 0b1
> > > +    SCR_EL3.API (bit 17) must be initialised to 0b1
> > > +  - If the kernel is entered at EL1:
> > > +    HCR_EL2.APK (bit 40) must be initialised to 0b1
> > > +    HCR_EL2.API (bit 41) must be initialised to 0b1
> > > +
> > 
> > 0b1 is quite confusing way to write 1.
> 
> Do you find 0x1 equally confusing?

It is slightly better. Still I'd not use it for describing single bit.

> 0bx is a pretty common way of describing bit-fields of a hardware
> register. It is also consistent with the rest of this document.

...and inconsistent with rest of the world :-).
									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html

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