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Message-ID: <CAEX_ruEw_0R4XZWXhdpDQHpEbf23CRCNvgQjAKiLs-TMycXd=A@mail.gmail.com>
Date: Mon, 22 Jan 2018 11:59:55 +0000
From: Samuel Neves <samuel.c.p.neves@...il.com>
To: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Andy Lutomirski <luto@...nel.org>, Jann Horn <jannh@...gle.com>,
Dan Williams <dan.j.williams@...el.com>, Thomas Gleixner <tglx@...utronix.de>,
linux-arch <linux-arch@...r.kernel.org>,
Kernel Hardening <kernel-hardening@...ts.openwall.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>, "the arch/x86 maintainers" <x86@...nel.org>,
Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>, Alan Cox <alan@...ux.intel.com>
Subject: Re: Re: [PATCH v4.1 07/10] x86: narrow out of
bounds syscalls to sys_read under speculation
On Mon, Jan 22, 2018 at 2:04 AM, Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
> However, I suspect it actually has a slightly higher register
> pressure, since you'd need to have that zero register (zero being the
> "safe" value), and the only good way to get a zero value is the xor
> thing, which affects flags and thus needs to be before the cmp.
>
> In contrast, the sbb trick has no early inputs needed.
On the flipside, sbb carries a false dependency [*] on the destination
register. Imagine something like
divq %rcx
...
cmpq %rdi, %rsi
sbbq %rax,%rax
sbb needs to wait not only for the comparison, but also for the
earlier unrelated slow division. On the other hand, zeroing with mov
or xor breaks dependencies on the destination register, making the
computation independent of what came before.
[*] Recent AMD chips are smart enough to understand the sbb r,r idiom
and ignore the value of r, but as far as I know none of the Intel
chips do.
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