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Message-ID: <alpine.DEB.2.20.1708251036150.5830@nuc-kabylake>
Date: Fri, 25 Aug 2017 10:38:18 -0500 (CDT)
From: Christopher Lameter <cl@...ux.com>
To: Boris Lukashev <blukashev@...pervictus.com>
cc: Ingo Molnar <mingo@...nel.org>, Thomas Garnier <thgarnie@...gle.com>,
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the arch/x86 maintainers <x86@...nel.org>,
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Peter Zijlstra <a.p.zijlstra@...llo.nl>, Borislav Petkov <bp@...en8.de>
Subject: Re: Re: x86: PIE support and option to extend
KASLR randomization
On Thu, 17 Aug 2017, Boris Lukashev wrote:
> Is the expectation then to have security functions also decrease size
> and operational latency? Seems a bit unrealistic if so.
> 1-2% performance hit on systems which have become at least several
> hundred % faster over recent years is not a significant performance
> regression compared to the baseline before.
Where do you get these fantastic numbers? Where can I buy a system like
that? Commonly we see regressions with single threaded integer
performance on most newer processor generations.
These hundreds of percent improvement can only come from floating point
performance using specialized instructions. There are only a very limited
number of applications that can make use of it.
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