[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20170809200755.11234-5-tycho@docker.com>
Date: Wed, 9 Aug 2017 14:07:49 -0600
From: Tycho Andersen <tycho@...ker.com>
To: linux-kernel@...r.kernel.org
Cc: linux-mm@...ck.org,
kernel-hardening@...ts.openwall.com,
Marco Benatto <marco.antonio.780@...il.com>,
Juerg Haefliger <juerg.haefliger@...onical.com>,
Juerg Haefliger <juerg.haefliger@....com>
Subject: [PATCH v5 04/10] arm64: Add __flush_tlb_one()
From: Juerg Haefliger <juerg.haefliger@....com>
Add a hook for flushing a single TLB entry on arm64.
Signed-off-by: Juerg Haefliger <juerg.haefliger@...onical.com>
Tested-by: Tycho Andersen <tycho@...ker.com>
---
arch/arm64/include/asm/tlbflush.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index af1c76981911..8e0c49105d3e 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -184,6 +184,14 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end
isb();
}
+static inline void __flush_tlb_one(unsigned long addr)
+{
+ dsb(ishst);
+ __tlbi(vaae1is, addr >> 12);
+ dsb(ish);
+ isb();
+}
+
/*
* Used to invalidate the TLB (walk caches) corresponding to intermediate page
* table levels (pgd/pud/pmd).
--
2.11.0
Powered by blists - more mailing lists
Confused about mailing lists and their use?
Read about mailing lists on Wikipedia
and check out these
guidelines on proper formatting of your messages.
