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Message-ID: <915a28c3-ec4d-2c19-17d1-ed47a6396ff9@arm.com> Date: Mon, 24 Jul 2017 11:54:58 +0100 From: Suzuki K Poulose <Suzuki.Poulose@....com> To: Mark Rutland <mark.rutland@....com>, linux-arm-kernel@...ts.infradead.org Cc: arnd@...db.de, catalin.marinas@....com, christoffer.dall@...aro.org, Dave.Martin@....com, jiong.wang@....com, kvmarm@...ts.cs.columbia.edu, linux-arch@...r.kernel.org, marc.zyngier@....com, will.deacon@....com, yao.qi@....com, linux-kernel@...r.kernel.org, kernel-hardening@...ts.openwall.com Subject: Re: [PATCH 04/11] arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits On 19/07/17 17:01, Mark Rutland wrote: > From ARMv8.3 onwards, ID_AA64ISAR1 is no longer entirely RES0, and now > has four fields describing the presence of pointer authentication > functionality: > > * APA - address authentication present, using an architected algorithm > * API - address authentication present, using an IMP DEF algorithm > * GPA - generic authentication present, using an architected algorithm > * GPI - generic authentication present, using an IMP DEF algoithm > > This patch adds the requisite definitions so that we can identify the > presence of this functionality. For the timebeing, the features are > hidden from userspace. > > Signed-off-by: Mark Rutland <mark.rutland@....com> > Cc: Catalin Marinas <catalin.marinas@....com> > Cc: Will Deacon <will.deacon@....com> > Cc: Suzuki K Poulose <suzuki.poulose@....com> > --- > arch/arm64/kernel/cpufeature.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9f9e0064..b23ad83 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -120,7 +120,11 @@ static int __init register_cpu_hwcaps_dumper(void) > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), > - ARM64_FTR_END, > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_GPI_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_GPA_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), > + ARM64_FTR_END > }; minor nit: Could we keep the fields in the order of their positions in the register ? With that, Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>
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