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Message-ID: <20170621090815.GC3768@arm.com>
Date: Wed, 21 Jun 2017 10:08:15 +0100
From: Will Deacon <will.deacon@....com>
To: Thomas Garnier <thgarnie@...gle.com>
Cc: Kees Cook <keescook@...omium.org>, Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, "H . Peter Anvin" <hpa@...or.com>,
Andy Lutomirski <luto@...nel.org>,
Paolo Bonzini <pbonzini@...hat.com>, Rik van Riel <riel@...hat.com>,
Oleg Nesterov <oleg@...hat.com>,
Josh Poimboeuf <jpoimboe@...hat.com>,
Petr Mladek <pmladek@...e.com>, Miroslav Benes <mbenes@...e.cz>,
Al Viro <viro@...iv.linux.org.uk>, Arnd Bergmann <arnd@...db.de>,
Dave Hansen <dave.hansen@...el.com>,
David Howells <dhowells@...hat.com>,
Russell King <linux@...linux.org.uk>,
Andy Lutomirski <luto@...capital.net>,
Will Drewry <wad@...omium.org>,
Catalin Marinas <catalin.marinas@....com>,
Mark Rutland <mark.rutland@....com>,
Pratyush Anand <panand@...hat.com>,
Chris Metcalf <cmetcalf@...lanox.com>,
"x86@...nel.org" <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
Linux API <linux-api@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>,
"kernel-hardening@...ts.openwall.com" <kernel-hardening@...ts.openwall.com>
Subject: Re: [PATCH v10 2/3] arm/syscalls: Check address limit on user-mode
return
On Tue, Jun 20, 2017 at 01:31:14PM -0700, Thomas Garnier wrote:
> On Tue, Jun 20, 2017 at 1:18 PM, Kees Cook <keescook@...omium.org> wrote:
> > On Wed, Jun 14, 2017 at 6:12 PM, Thomas Garnier <thgarnie@...gle.com> wrote:
> >> diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
> >> index eb5cd77bf1d8..e33c32d56193 100644
> >> --- a/arch/arm/kernel/entry-common.S
> >> +++ b/arch/arm/kernel/entry-common.S
> >> @@ -41,7 +41,9 @@ ret_fast_syscall:
> >> UNWIND(.cantunwind )
> >> disable_irq_notrace @ disable interrupts
> >> ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
> >> - tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
> >> + tst r1, #_TIF_SYSCALL_WORK
> >> + bne fast_work_pending
> >> + tst r1, #_TIF_WORK_MASK
> >
> > (IIUC) MOV32 is 2 cycles (MOVW, MOVT), and each TST above is 1 cycle
> > and each BNE is 1 cycle (when not taken). So:
> >
> > mov32 r2, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
> > tst r1, r2
> > bne fast_work_pending
> >
> > is 4 cycles and tst, bne, tst, bne is also 4 cycles. Would mov32 be
> > more readable (since it keeps the flags together)?
>
> I guess it would be more readable. Any opinion from the arm folks?
The mov32 sequence is probably better, but statically attributing cycles
on a per instruction basis is pretty futile on modern CPUs.
Will
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