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Message-ID: <20161110225031.GA26751@worktop>
Date: Thu, 10 Nov 2016 23:50:31 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Elena Reshetova <elena.reshetova@...el.com>
Cc: kernel-hardening@...ts.openwall.com, keescook@...omium.org,
arnd@...db.de, tglx@...utronix.de, mingo@...hat.com,
h.peter.anvin@...el.com, will.deacon@....com,
Hans Liljestrand <ishkamiel@...il.com>,
David Windsor <dwindsor@...il.com>
Subject: Re: [RFC v4 PATCH 12/13] x86: implementation for HARDENED_ATOMIC
On Thu, Nov 10, 2016 at 09:40:46PM +0100, Peter Zijlstra wrote:
> On Thu, Nov 10, 2016 at 10:24:47PM +0200, Elena Reshetova wrote:
> > static __always_inline void atomic_add(int i, atomic_t *v)
> > {
> > + asm volatile(LOCK_PREFIX "addl %1,%0\n"
> > +
> > +#ifdef CONFIG_HARDENED_ATOMIC
> > + "jno 0f\n"
> > + LOCK_PREFIX "subl %1,%0\n"
> > + "int $4\n0:\n"
> > + _ASM_EXTABLE(0b, 0b)
>
>
> This is unreadable gunk.
Worse, this is fundamentally racy and therefore not a proper atomic at
all.
The only way to do this is a cmpxchg loop and not issue the result on
overflow. Of course, that would completely suck performance wise, but
having a non atomic atomic blows more.
> > +#endif
> > +
> > : "+m" (v->counter)
> > : "ir" (i));
> > }
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