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Message-ID: <67ef8651-1d11-e54d-535e-0a24b1cbaf2b@gruss.cc>
Date: Sat, 29 Oct 2016 22:14:23 +0200
From: Daniel Gruss <daniel@...ss.cc>
To: kernel-hardening@...ts.openwall.com
Subject: Re: rowhammer protection [was Re: Getting
interrupt every million cache misses]
On 29.10.2016 22:05, Daniel Gruss wrote:
> I'm very confident you're not successful the way you['re] starting ;)
Just to give a reason to that: on many systems you can have bitflips
with far less than 1 or 2 million cache misses.
https://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf reports as
little as 139K accesses (-> cache misses) to be sufficient on one of
their systems and on one of my systems I can have a bit flip with as
little as 78K cache misses (double sided hammering).
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