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Message-ID: <20161028184804.GN3142@twins.programming.kicks-ass.net>
Date: Fri, 28 Oct 2016 20:48:04 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Pavel Machek <pavel@....cz>
Cc: Mark Rutland <mark.rutland@....com>, Kees Cook <keescook@...omium.org>,
Arnaldo Carvalho de Melo <acme@...hat.com>,
kernel list <linux-kernel@...r.kernel.org>,
Ingo Molnar <mingo@...hat.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
"kernel-hardening@...ts.openwall.com" <kernel-hardening@...ts.openwall.com>
Subject: Re: rowhammer protection [was Re: Getting
interrupt every million cache misses]
On Fri, Oct 28, 2016 at 08:30:14PM +0200, Pavel Machek wrote:
> Would you (or someone) have pointer to good documentation source on
> available performance counters?
The Intel SDM has a section on them and the AMD Bios and Kernel
Developers Guide does too.
That is, they contain lists of available counters for the various parts
from these vendors and that's pretty much all there is.
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