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Date: Wed, 9 Sep 2015 19:51:38 +0300
From: Solar Designer <>
Subject: Re: SHA-1 H()

On Wed, Sep 09, 2015 at 11:43:41PM +0800, Lei Zhang wrote:
> On Sep 8, 2015, at 4:47 PM, Solar Designer <> wrote:
> > On Tue, Sep 08, 2015 at 03:04:57PM +0800, Lei Zhang wrote:
> >> On AltiVec (4xOMP):
> > 
> > Is this 4 threads likely across different CPU cores?
> I think so. The benchmark results just fluctuated too bad when I utilize the maximum number of hardware threads, so I switched to a small number of threads, without binding them to a specific core though.

Have you also tried e.g. staying just one core's worth (8 threads) below
the maximum?  And things like GOMP_SPINCOUNT=10000 and
GOMP_CPU_AFFINITY=0-155 (or whatever is the full range of logical CPU
numbers).  Of course, these things only make sense if the system is
otherwise idle.  If you can actually see where other load comes from,
then you need to reduce your use of the cores accordingly.

> >> There's no significant change on Altivec,
> > 
> > OK, but you need to run 8 threads/core benchmarks.
> Why? Our ZedBoard has only two cores.

That comment of mine only applied to your "There's no significant change
on Altivec" - thus, it didn't apply to ZedBoard.

> > Also, as I suggested in the "MD5 on XOP, NEON, AltiVec" thread:
> > 
> > "[...] we'll need to revise MD5_I in simd-intrinsics.c to use [...]
> > the obvious expression with OR-NOT on NEON and AltiVec (IIRC, those
> > archs have OR-NOT, which might be lower latency than select)."
> I just checked the manuals. NEON does support OR-NOT, but AltiVec seems to only support NOT-OR (~(a|b)). So only NEON can benefit from this optimization perhaps.

Oh, OK.  MD5_I is also implementable with XNOR, but I think AltiVec
lacks that too.  That's not a big deal since it has bitselect.


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